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| PIC18F87K22 Datasheet, PDF (251/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology | |||
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PIC18F87K22 FAMILY
FIGURE 19-2:
COMPARE MODE OPERATION BLOCK DIAGRAM
CCPR5H CCPR5L
Set CCP5IF
Comparator
Compare
Match
TMR1H TMR1L
0
Special Event Trigger
(Timer1/5 Reset)
Output
Logic
4
CCP5CON<3:0>
SQ
R
CCP5 Pin
TRIS
Output Enable
TMR5H
TMR5L
1
C5TSEL0
0
TMR1H
TMR1L
1
TMR5H
TMR5L
C4TSEL1
C4TSEL0
Special Event Trigger
(Timer1/Timer3 Reset, A/D Trigger)
Comparator
Compare
Match
CCPR4H CCPR4L
Set CCP4IF
Output
Logic
4
CCP4CON<3:0>
SQ
R
CCP4 Pin
TRIS
Output Enable
Note:
This block diagram uses CCP4 and CCP5 and their appropriate timers as an example. For details on all of
the CCP modules and their timer assignments, see Table 19-2 and Table 19-3.
TABLE 19-5: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3/5/7
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF INT0IF
RBIF
RCON
PIR4
PIE4
IPR4
IPEN SBOREN
CCP10IF(1) CCP9IF(1)
CCP10IE(1) CCP9IE(1)
CCP10IP(1) CCP9IP(1)
CM
CCP8IF
CCP8IE
CCP8IP
RI
CCP7IF
CCP7IE
CCP7IP
TO
CCP6IF
CCP6IE
CCP6IP
PD
CCP5IF
CCP5IE
CCP5IP
POR
CCP4IF
CCP4IE
CCP4IP
BOR
CCP3IF
CCP3IE
CCP3IP
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
TRISE
TRISH(2)
TRISE7
TRISH7
TRISE6
TRISH6
TRISE5
TRISH5
TRISE4
TRISH4
TRISE3
TRISH3
TRISE2
TRISH2
TRISE1
TRISH1
TRISE0
TRISH0
TMR1L
Timer1 Register Low Byte
Legend: â = unimplemented, read as â0â. Shaded cells are not used by Capture/Compare or Timer1/3/5/7.
Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18F65K22 and PIC18F85K22).
2: Unimplemented on 64-pin devices (PIC18F65K22, PIC18F66K22 and PIC18F67K22).
ï£ 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 251
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