PIC18F87K22 Datasheet, PDF (200/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

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The Lower Drive Level mode is highly optimized for
extremely low-power consumption. It is not intended to
drive all types of 32.768 kHz crystals. In the Low Drive
Level mode, the crystal oscillator circuit may not work
correctly if excessively large discrete capacitors are
placed on the SOSCO and SOSCI pins. This mode is
designed to work only with discrete capacitances of
approximately 3 pF-10 pF on each pin.
Crystal manufacturers usually specify a CL (Load
Capacitance) rating for their crystals. This value is
related to, but not necessarily the same as, the values
that should be used for C1 and C2 in Figure 14-2.
For more details on selecting the optimum C1 and C2
for a given crystal, see the crystal manufacturer’s appli-
cations information. The optimum value depends in
part on the amount of parasitic capacitance in the
circuit, which is often unknown. For that reason, it is
highly recommended that thorough testing and valida-
tion of the oscillator be performed after values have
been selected.
14.5.1
USING SOSC AS A
CLOCK SOURCE
The SOSC oscillator is also available as a clock source
in power-managed modes. By setting the clock select
bits, SCS<1:0> (OSCCON<1:0>), to ‘01’, the device
switches to SEC_RUN mode and both the CPU and
peripherals are clocked from the SOSC oscillator. If the
IDLEN bit (OSCCON<7>) is cleared and a SLEEP
instruction is executed, the device enters SEC_IDLE
mode. Additional details are available in Section 4.0
“Power-Managed Modes”.
Whenever the SOSC oscillator is providing the clock
source, the SOSC System Clock Status flag,
SOSCRUN (OSCCON2<6>), is set. This can be used
to determine the controller’s current clocking mode. It
can also indicate the clock source currently being used
by the Fail-Safe Clock Monitor.
If the Clock Monitor is enabled and the SOSC oscillator
fails while providing the clock, polling the SOCSRUN
bit will indicate whether the clock is being provided by
the SOSC oscillator or another source.
14.5.2
SOSC OSCILLATOR LAYOUT
CONSIDERATIONS
The SOSC oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity. This is especially true when
the oscillator is configured for extremely low-power
mode, SOSCSEL<1:0> (CONFIG1L<4:3>) = 01.
The oscillator circuit, displayed in Figure 14-2, should
be located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the
oscillator, it may help to have a grounded guard ring
around the oscillator circuit. The guard, as displayed in
Figure 14-3, could be used on a single-sided PCB or in
addition to a ground plane. (Examples of a high-speed
circuit include the ECCP1 pin, in Output Compare or
PWM mode, or the primary oscillator, using the OSC2
pin.)
FIGURE 14-3:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
VDD
VSS
OSC1
OSC2
RC0
RC1
Note: Not drawn to scale.
RC2
In the Low Drive Level mode, SOSCSEL<1:0> = 01, it is
critical that RC2 I/O pin signals be kept away from the
oscillator circuit. Configuring RC2 as a digital output, and
toggling it, can potentially disturb the oscillator circuit,
even with a relatively good PCB layout. If possible, either
leave RC2 unused or use it as an input pin with a slew
rate limited signal source. If RC2 must be used as a
digital output, it may be necessary to use the Higher
Drive Level Oscillator mode (SOSCSEL<1:0> = 11) with
many PCB layouts.
Even in the Higher Drive Level mode, careful layout
procedures should still be followed when designing the
oscillator circuit.
In addition to dV/dt induced noise considerations, it is
important to ensure that the circuit board is clean. Even
a very small amount of conductive soldering flux
residue can cause PCB leakage currents that can
overwhelm the oscillator circuit.
14.6 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
DS39960B-page 200
Preliminary
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