PIC18F87K22 Datasheet, PDF (172/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
12.4 PORTC, TRISC and
LATC Registers
PORTC is an eight-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISC and LATC. Only PORTC pins, RC2 through
RC7, are digital only pins.
PORTC is multiplexed with ECCP, MSSP and EUSART
peripheral functions (Table 12-5). The pins have
Schmitt Trigger input buffers. The pins for ECCP, SPI
and EUSART are also configurable for open-drain out-
put whenever these functions are active. Open-drain
configuration is selected by setting the SPIOD,
CCPxOD and U1OD control bits in the registers,
ODCON1 and ODCON3.
RC1 is normally configured as the default peripheral
pin for the ECCP2 module. Assignment of ECCP2 is
controlled by Configuration bit, CCP2MX (default state,
CCP2MX = 1).
When enabling peripheral functions, use care in defin-
ing TRIS bits for each PORTC pin. Some peripherals
can override the TRIS bit to make a pin an output or
input. Consult the corresponding peripheral section for
the correct TRIS bit settings.
Note: These pins are configured as digital inputs
on any device Reset.
The contents of the TRISC register are affected by
peripheral overrides. Reading TRISC always returns
the current contents, even though a peripheral device
may be overriding one or more of the pins.
EXAMPLE 12-3: INITIALIZING PORTC
CLRF
CLRF
MOVLW
MOVWF
PORTC
LATC
0CFh
TRISC
; Initialize PORTC by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
TABLE 12-5: PORTC FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RC0/SOSCO/
SCLKI/
RC0
0
O DIG LATC<0> data output.
1
I ST PORTC<0> data input.
SOSCO 1
I ST SOSC oscillator output.
SCLKI
1
I ST Digital clock input; enabled when SOSC oscillator disabled.
RC1/SOSCI/
ECCP2/P2A
RC1
0
O DIG LATC<1> data output.
1
I ST PORTC<1> data input.
SOSCI
x
ECCP2⁽¹⁾ 0
I ANA SOSC oscillator input.
O DIG ECCP2 compare output and ECCP2 PWM output.
Takes priority over port data.
1
I ST ECCP2 Capture input.
P2A
0
O DIG ECCP2 Enhanced PWM output, Channel A.
May be configured for tri-state during Enhanced PWM shutdown events. Takes
priority over port data.
RC2/ECCP1/
P1A
RC2
0
O DIG LATC<2> data output.
1
I ST PORTC<2> data input.
ECCP1
0
O DIG ECCP1 compare output and ECCP1 PWM output. Takes priority over port data.
1
I ST ECCP1 capture input.
P1A
0
O DIG ECCP1 enhanced PWM output, Channel A.
May be configured for tri-state during Enhanced PWM shutdown events. Takes
priority over port data.
Legend:
Note 1:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, TTL = TTL Buffer Input,
I²C = I²C™/SMBus Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
DS39960B-page 172
Preliminary
 2010 Microchip Technology Inc.