PIC18F87K22 Datasheet, PDF (170/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
12.3 PORTB, TRISB and
LATB Registers
PORTB is an eight-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISB and LATB. All pins on PORTB are digital only.
EXAMPLE 12-2: INITIALIZING PORTB
CLRF
CLRF
MOVLW
MOVWF
PORTB
LATB
0CFh
TRISB
; Initialize PORTB by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB<7:4>) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur; any RB<7:4>
pin configured as an output being excluded from the
interrupt-on-change comparison.
Comparisons with the input pins (of RB<7:4>) are
made with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB<7:4> are ORed
together to generate the RB Port Change Interrupt with
Flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from
power-managed modes. To clear the interrupt in the
Interrupt Service Routine:
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will
end the mismatch condition.
b) Wait one instruction cycle (such as executing a
NOP instruction).
c) Clear flag bit, RBIF.
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after one TCY delay.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
The RB<3:2> pins are multiplexed as CTMU edge
inputs. RB5 has an additional function for Timer3 and
Timer1. It can be configured for Timer3 clock input or
Timer1 external clock gate input.
TABLE 12-3: PORTB FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RB0/INT0/FLT0
RB0
0
O
DIG LATB<0> data output.
1
I
TTL PORTB<0> data input; weak pull-up when RBPU bit is cleared.
INT0
1
I
ST External Interrupt 0 input.
FLT0
x
I
ST Enhanced PWM Fault input for ECCPx.
RB1/INT1
RB1
0
O
DIG LATB<1> data output.
1
I
TTL PORTB<1> data input; weak pull-up when RBPU bit is cleared.
INT1
1
I
ST External Interrupt 1 input.
RB2/INT2/CTED1
RB2
0
O
DIG LATB<2> data output.
1
I
TTL PORTB<2> data input; weak pull-up when RBPU bit is cleared.
INT2
1
I
ST External Interrupt 2 input.
CTED1
x
I
ST CTMU Edge 1 input.
Legend:
Note 1:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Extended Microcontroller mode.
DS39960B-page 170
Preliminary
 2010 Microchip Technology Inc.