PIC18F87K22 Datasheet, PDF (221/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
17.0 TIMER4/6/8/10/12 MODULES
The Timer4/6/8/10/12 timer modules have the following
features:
• Eight-bit Timer register (TMRx)
• Eight-bit Period register (PRx)
• Readable and writable (all registers)
• Software programmable prescaler (1:1, 1:4, 1:16)
• Software programmable postscaler (1:1 to 1:16)
• Interrupt on TMRx match of PRx
Timer10 and Timer12 are unimplemented for devices
with program memory of 32 Kbytes (PIC18FX5K22).
Note: Throughout this section, generic references
are used for register and bit names that are the
same, except for an ‘x’ variable that indicates
the item’s association with the Timer4, Timer6,
Timer8, Timer10 or Timer12 module. For
example, the control register is named TxCON
and refers to T4CON, T6CON, T8CON,
T10CON and T12CON.
The Timer4/6/8/10/12 modules have a control register
shown in Register 17-1. Timer4/6/8/10/12 can be shut
off by clearing control bit, TMRxON (TxCON<2>), to
minimize power consumption. The prescaler and post-
scaler selection of Timer4/6/8/10/12 also are controlled
by this register. Figure 17-1 is a simplified block
diagram of the Timer4/6/8/10/12 modules.
17.1 Timer4/6/8/10/12 Operation
Timer4/6/8/10/12 can be used as the PWM time base
for the PWM mode of the ECCP modules. The TMRx
registers are readable and writable, and are cleared on
any device Reset. The input clock (FOSC/4) has a
prescale option of 1:1, 1:4 or 1:16, selected by control
bits, TxCKPS<1:0> (TxCON<1:0>). The match output
of TMRx goes through a four-bit postscaler (that gives
a 1:1 to 1:16 inclusive scaling) to generate a TMRx
interrupt, latched in the flag bit, TMRxIF. Table 17-1
gives each module’s flag bit.
TABLE 17-1: TIMER4/6/8/10/12 FLAG BITS
Timer
Module
Flag Bit
PIR5<x>
Timer
Module
Flag Bit
PIR5<x>
4
0
10
5
6
2
12
6
8
4
The interrupt can be enabled or disabled by setting or
clearing the Timerx Interrupt Enable bit (TMRxIE),
shown in Table 17-2.
TABLE 17-2: TIMER4/6/8/10/12 INTERRUPT
ENABLE BITS
Timer
Module
Flag Bit
PIE5<x>
Timer
Module
Flag Bit
PIE5<x>
4
0
10
5
6
2
12
6
8
4
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMRx register
• A write to the TxCON register
• Any device Reset – Power-on Reset (POR),
MCLR Reset, Watchdog Timer Reset (WDTR) or
Brown-out Reset (BOR)
A TMRx is not cleared when a TxCON is written.
Note:
The CCP and ECCP modules use Timers,
1 through 8, for some modes. The assign-
ment of a particular timer to a CCP/ECCP
module is determined by the Timer to CCP
enable bits in the CCPTMRSx registers.
For more details, see Register 20-2,
Register 19-2 and Register 19-3.
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 221