PIC18F87K22 Datasheet, PDF (71/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
5.0 RESET
The PIC18F87K22 family of devices differentiates
between various kinds of Reset:
a) Power-on Reset (POR)
b) MCLR Reset during normal operation
c) MCLR Reset during power-managed modes
d) Watchdog Timer (WDT) Reset (during
execution)
e) Configuration Mismatch (CM) Reset
f) Brown-out Reset (BOR)
g) RESET Instruction
h) Stack Full Reset
i) Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 6.1.3.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 28.2 “Watchdog
Timer (WDT)”.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 5-1.
5.1 RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event.
The state of these flag bits, taken together, can be read
to indicate the type of Reset that just occurred. This is
described in more detail in Section 5.7 “Reset State
of Registers”.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
in Section 11.0 “Interrupts”.
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET Instruction
Configuration Word Mismatch
Stack ^{Stack Full/Underflow Reset}
Pointer
External Reset
MCLR
VDD
( )_IDLE
Sleep
WDT
Time-out
VDD Rise POR Pulse
Detect
Brown-out
Reset
PWRT
32 s
PWRT 66 ms
LF-INTOSC
11-Bit Ripple Counter
S
Chip_Reset
R
Q
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 71