PIC18F87K22 Datasheet, PDF(277/548 Page) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

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PIC18F87K22 Datasheet, PDF (277/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

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PIC18F87K22 FAMILY

20.4.8

OPERATION IN POWER-MANAGED

MODES

In Sleep mode, all clock sources are disabled.

Timer2/4/6/8 will not increment and the state of the

module will not change. If the ECCPx pin is driving a

value, it will continue to drive that value. When the

device wakes up, it will continue from this state. If

Two-Speed Start-ups are enabled, the initial start-up

frequency from HF-INTOSC and the postscaler may

not be stable immediately.

In PRI_IDLE mode, the primary clock will continue to

clock the ECCPx module without change.

20.4.8.1 Operation with Fail-Safe

Clock Monitor (FSCM)

If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock

failure will force the device into the power-managed

RC_RUN mode and the OSCFIF bit of the PIR2 register

will be set. The ECCPx will then be clocked from the

internal oscillator clock source, which may have a

different clock frequency than the primary clock.

20.4.9 EFFECTS OF A RESET

Both Power-on Reset and subsequent Resets will force

all ports to Input mode and the ECCP registers to their

Reset states.

This forces the ECCP module to reset to a state

compatible with previous, non-enhanced CCP modules

used on other PIC18 and PIC16 devices.

TABLE 20-4: REGISTERS ASSOCIATED WITH ECCP1/2/3 MODULE AND

TIMER1/2/3/4/6/8/10/12

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

RCON

IPEN

SBOREN

CM

RI

TO

PD

POR

BOR

PIR3

PIR4

TMR5GIF

CCP10IF(1)

â

CCP9IF(1)

RC2IF

CCP8IF

TX2IF

CCP7IF

CTMUIF

CCP6IF

CCP2IF

CCP5IF

CCP1IF

CCP4IF

RTCCIF

CCP3IF

PIE3

PIE4

TMR5GIE

CCP10IE(1)

â

CCP9IE(1)

RC2IE

CCP8IE

TX2IE

CCP7IE

CTMUIE

CCP6IE

CCP2IE

CCP5IE

CCP1IE

CCP4IE

RTCCIE

CCP3IE

IPR3

IPR4

TMR5GIP

CCP10IP(1)

â

CCP9IP(1)

RC2IP

CCP8IP

TX2IP

CCP7IP

CTMUIP

CCP6IP

CCP2IP

CCP5IP

CCP1IP

CCP4IP

RTCCIP

CCP3IP

TRISB

TRISB7

TRISB6

TRISB5

TRISB4

TRISB3

TRISB2

TRISB1 TRISB0

TRISC

TRISC7

TRISC6

TRISC5

TRISC4

TRISC3 TRISC2 TRISC1 TRISC0

TRISE

TRISH(2)

TRISE7

TRISH7

TRISE6

TRISH6

TRISE5

TRISH5

TRISE4

TRISH4

TRISE3

TRISH3

TRISE2

TRISH2

TRISE1

TRISH1

TRISE0

TRISH0

TMR1H

Timer1 Register High Byte

TMR1L

Timer1 Register Low Byte

TMR2

Timer2 Register

TMR3H

Timer3 Register High Byte

TMR3L

Timer3 Register Low Byte

TMR4

Timer4 Register

TMR6

Timer6 Register

TMR8

TMR10(1)

TMR12(1)

Timer8 Register

TMR10 Register

TMR10 Register

PR2

Timer2 Period Register

PR4

Timer4 Period Register

PR6

Timer6 Period Register

PR8

PR10(1)

PR12(1)

Timer8 Period Register

Timer10 Period Register

Timer12 Period Register

Note 1: Unimplemented on devices with a program memory of 32 Kbytes (PIC18F65K22 and PIC18F85K22).

2: Unimplemented on 64-pin devices (PIC18F65K22, PIC18F66K22 and PIC18F67K22).

ï£ 2010 Microchip Technology Inc.

Preliminary

DS39960B-page 277

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