PIC18F87K22 Datasheet, PDF (516/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
FIGURE 31-20:
SCLx
SDAx
In
SDAx
Out
I²C™ BUS DATA TIMING
103
100
90
106
91
101
107
109
109
Note: Refer to Figure 31-3 for load conditions.
102
92
110
TABLE 31-21: I²C™ BUS DATA REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
100
THIGH Clock High Time
100 kHz mode
4.0
—
s
400 kHz mode
0.6
—
s
MSSP module
1.5 TCY
—
101
TLOW
Clock Low Time
100 kHz mode
4.7
—
s
400 kHz mode
1.3
—
s
MSSP module
1.5 TCY
—
102
TR
SDAx and SCLx Rise Time 100 kHz mode
—
1000 ns
400 kHz mode 20 + 0.1 CB 300
ns CB is specified to be from
10 to 400 pF
103
TF
SDAx and SCLx Fall Time 100 kHz mode
—
300 ns
400 kHz mode 20 + 0.1 CB 300
ns CB is specified to be from
10 to 400 pF
90
TSU:STA Start Condition Setup Time 100 kHz mode
4.7
—
s Only relevant for Repeated
400 kHz mode
0.6
—
s ^{Start condition}
91
THD:STA Start Condition Hold Time 100 kHz mode
4.0
—
s After this period, the first clock
400 kHz mode
0.6
—
s ^{pulse is generated}
106
THD:DAT Data Input Hold Time
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
s
107
TSU:DAT Data Input Setup Time
100 kHz mode
250
—
ns (Note 2)
400 kHz mode
100
—
ns
92
TSU:STO Stop Condition Setup Time 100 kHz mode
4.7
—
s
400 kHz mode
0.6
—
s
109
TAA
Output Valid from Clock 100 kHz mode
—
3500 ns (Note 1)
400 kHz mode
—
—
ns
110
TBUF
Bus Free Time
100 kHz mode
4.7
—
s Time the bus must be free before
400 kHz mode
1.3
—
s ^{a new transmission can start}
D102 CB
Bus Capacitive Loading
—
400 pF
Note 1:
2:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of
the falling edge of SCLx to avoid unintended generation of Start or Stop conditions.
A Fast mode I²C™ bus device can be used in a Standard mode I²C bus system, but the requirement, TSU:DAT  250 ns,
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLx signal. If
such a device does stretch the LOW period of the SCLx signal, it must output the next data bit to the SDAx line,
TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification), before the SCLx line
is released.
DS39960B-page 516
Preliminary
 2010 Microchip Technology Inc.