PIC18F87K22 Datasheet, PDF (399/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
27.9 Operation During Sleep/Idle Modes
27.9.1 SLEEP MODE
When the device enters any Sleep mode, the CTMU
module current source is always disabled. If the CTMU
is performing an operation that depends on the current
source when Sleep mode is invoked, the operation may
not terminate correctly. Capacitance and time
measurements may return erroneous values.
27.9.2 IDLE MODE
The behavior of the CTMU in Idle mode is determined
by the CTMUSIDL bit (CTMUCONH<5>). If CTMUSIDL
is cleared, the module will continue to operate in Idle
mode. If CTMUSIDL is set, the module’s current source
is disabled when the device enters Idle mode. In this
case, if the module is performing an operation when
Idle mode is invoked, the results will be similar to those
with Sleep mode.
27.10 Effects of a Reset on CTMU
Upon Reset, all registers of the CTMU are cleared. This
disables the CTMU module, turns off its current source
and returns all configuration options to their default set-
tings. The module needs to be re-initialized following
any Reset.
If the CTMU is in the process of taking a measurement
at the time of Reset, the measurement will be lost. A
partial charge may exist on the circuit that was being
measured, which should be properly discharged before
the CTMU makes subsequent attempts to make a
measurement. The circuit is discharged by setting and
clearing the IDISSEN bit (CTMUCONH<1>) while the
A/D Converter is connected to the appropriate channel.
TABLE 27-1: REGISTERS ASSOCIATED WITH CTMU MODULE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CTMUCONH CTMUEN
—
CTMUSIDL
TGEN
EDGEN EDGSEQEN
CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0
CTMUICON
ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
PIR3
TMR5GIF
—
RC2IF
TX2IF
CTMUIF
CCP2IF
PIE3
TMR5GIE
—
RC2IE
TX2IE
CTMUIE
CCP2IE
IPR3
TMR5GIP
—
RC2IP
TX2IP
CTMUIP
CCP2IP
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
IDISSEN
EDG2STAT
IRNG1
CCP1IF
CCP1IE
CCP1IP
CTTRIG
EDG1STAT
IRNG0
RTCCIF
RTCCIE
RTCCIP
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 399