PIC18F87K22 Datasheet, PDF (39/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
2.4 Voltage Regulator Pins (ENVREG
and VCAP/VDDCORE)
The on-chip voltage regulator enable pin, ENVREG,
must always be connected directly to either a supply
voltage or to ground. Tying ENVREG to VDD enables
the regulator, while tying it to ground disables the
regulator. Refer to Section 28.3 “On-Chip Voltage
Regulator” for details on connecting and using the
on-chip regulator.
When the regulator is enabled, a low-ESR (< 5Ω)
capacitor is required on the VCAP/VDDCORE pin to
stabilize the voltage regulator output voltage. The
VCAP/VDDCORE pin must not be connected to VDD and
must use a capacitor of 10 F connected to ground. The
type can be ceramic or tantalum. A suitable example is
the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or
equivalent. Designers may use Figure 2-3 to evaluate
ESR equivalence of candidate devices.
It is recommended that the trace length not exceed
0.25 inch (6 mm). Refer to Section 31.0 “Electrical
Characteristics” for additional information.
When the regulator is disabled, a 0.1 F capacitor
should be connected from the VCAP/VDDCORE pin to
ground. This capacitor’s characteristics must be similar
to those of the “decoupling” capacitors explained in
Section 2.2.1 “Decoupling Capacitors”. For details
on the VDD requirement, when the regulator is
disabled, see parameter D001 in Section 31.0
“Electrical Characteristics”.
Some PIC18FXXKXX families or some devices within
a family do not provide the option of enabling or
disabling the on-chip voltage regulator:
• Some devices (with the name, PIC18LFXXKXX)
permanently disable the voltage regulator.
These devices’ do not have the ENVREG pin and
require a 0.1 F capacitor on the VCAP/VDDCORE
pin. The VDD level of these devices must comply
with the “voltage regulator disabled” specification
for parameter D001, in Section 31.0 “Electrical
Characteristics”.
• Some devices permanently enable the voltage
regulator.
These devices also do not have the ENVREG pin.
The 10F capacitor is still required on the
VCAP/VDDCORE pin.
For details on all members of the PIC18F87K22 family,
see Section 28.3 “On-Chip Voltage Regulator”.
FIGURE 2-3:
10
1
FREQUENCY vs. ESR
PERFORMANCE FOR
SUGGESTED VCAP
0.1
0.01
0.001
0.01
0.1
1
10
100
Frequency (MHz)
1000 10,000
Note:
Data for Murata GRM21BF50J106ZE01 shown.
Measurements at 25°C, 0V DC bias.
2.5 ICSP Pins
The PGC and PGD pins are used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes. It
is recommended to keep the trace length between the
ICSP connector and the ICSP pins on the device as
short as possible. If the ICSP connector is expected to
experience an ESD event, a series resistor is recom-
mended, with the value in the range of a few tens of
ohms, not to exceed 100Ω.
Pull-up resistors, series diodes and capacitors on the
PGC and PGD pins are not recommended as they will
interfere with the programmer/debugger communica-
tions to the device. If such discrete components are an
application requirement, they should be removed from
the circuit during programming and debugging. Alter-
natively, refer to the AC/DC characteristics and timing
requirements information in the respective device
Flash programming specification for information on
capacitive loading limits, and pin input voltage high
(VIH) and input low (VIL) requirements.
For device emulation, ensure that the “Communication
Channel Select” (i.e., PGCx/PGDx pins) programmed
into the device matches the physical connections for
the ICSP to the Microchip debugger/emulator tool.
For more information on available Microchip
development tools connection requirements, refer to
Section 30.0 “Development Support”.
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 39