PIC18F87K22 Datasheet, PDF(219/548 Page) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

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PIC18F87K22 Datasheet, PDF (219/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

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PIC18F87K22 FAMILY

16.6 Timer3/5/7 Interrupt

The TMRx register pair (TMRxH:TMRxL) increments

from 0000h to FFFFh and overflows to 0000h. The

Timerx interrupt, if enabled, is generated on overflow

and is latched in the interrupt flag bit, TMRxIF.

Table 16-3 gives each moduleâs flag bit.

TABLE 16-3: TIMER3/5/7 INTERRUPT

FLAG BITS

Timer Module

Flag Bit

3

PIR2<1>

5

PIR5<1>

7

PIR5<3>

This interrupt can be enabled or disabled by setting or

clearing the TMRxIE bit, respectively. Table 16-4 gives

each moduleâs enable bit.

TABLE 16-4: TIMER3/5/7 INTERRUPT

ENABLE BITS

Timer Module

Flag Bit

3

PIE2<1>

5

PIE5<1>

7

PIE5<3>

16.7 Resetting Timer3/5/7 Using the

ECCP Special Event Trigger

If the ECCP modules are configured to use Timerx and

to generate a Special Event Trigger in Compare mode

(CCPxM<3:0> = 1011), this signal will reset Timerx. The

trigger from ECCP2 will also start an A/D conversion if

the A/D module is enabled (For more information, see

Section 20.3.4 âSpecial Event Triggerâ.)

The module must be configured as either a timer or

synchronous counter to take advantage of this feature.

When used this way, the CCPRxH:CCPRxL register

pair effectively becomes a Period register for Timerx.

If Timerx is running in Asynchronous Counter mode,

the Reset operation may not work.

In the event that a write to Timerx coincides with a

Special Event Trigger from an ECCP module, the write

will take precedence.

Note:

The Special Event Triggers from the

ECCPx module will only clear the TMR3

registerâs content, but not set the TMR3IF

interrupt flag bit (PIR1<0>).

Note:

The CCP and ECCP modules use Timers,

1 through 8, for some modes. The assign-

ment of a particular timer to a CCP/ECCP

module is determined by the Timer to CCP

enable bits in the CCPTMRSx registers.

For more details, see Register 20-2,

Register 19-2 and Register 19-3.

ï£ 2010 Microchip Technology Inc.

Preliminary

DS39960B-page 219

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