PIC18F87K22 Datasheet, PDF (53/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
3.8 Effects of Power-Managed Modes
on the Various Clock Sources
When PRI_IDLE mode is selected, the designated pri-
mary oscillator continues to run without interruption.
For all other power-managed modes, the oscillator
using the OSC1 pin is disabled. The OSC1 pin (and
OSC2 pin if used by the oscillator) will stop oscillating.
In secondary clock modes (SEC_RUN and
SEC_IDLE), the SOSC oscillator is operating and
providing the device clock. The SOSC oscillator may
also run in all power-managed modes if required to
clock SOSC.
In RC_RUN and RC_IDLE modes, the internal
oscillator provides the device clock source. The 31 kHz
LF-INTOSC output can be used directly to provide the
clock and may be enabled to support various special
features, regardless of the power-managed mode (see
Section 28.2 “Watchdog Timer (WDT)” through
Section 28.5 “Fail-Safe Clock Monitor” for more
information on WDT, Fail-Safe Clock Monitor and
Two-Speed Start-up).
If the Sleep mode is selected, all clock sources are
stopped. Since all the transistor switching currents
have been stopped, Sleep mode achieves the lowest
current consumption of the device (only leakage
currents).
Enabling any on-chip feature that will operate during
Sleep will increase the current consumed during Sleep.
The INTOSC is required to support WDT operation.
The SOSC oscillator may be operating to support a
Real-Time Clock (RTC). Other features may be operat-
ing that do not require a device clock source (i.e.,
MSSP slave, INTx pins and others). Peripherals that
may add significant current consumption are listed in
Section 31.2 “DC Characteristics: Power-Down and
Supply Current PIC18F87K22 Family (Industrial)”.
3.9 Power-up Delays
Power-up delays are controlled by two timers, so that
no external Reset circuitry is required for most applica-
tions. The delays ensure that the device is kept in
Reset until the device power supply is stable under nor-
mal circumstances and the primary clock is operating
and stable. For additional information on power-up
delays, see Section 5.6 “Power-up Timer (PWRT)”.
The first timer is the Power-up Timer (PWRT), which
provides a fixed delay on power-up time of about 64 ms
(parameter 33, Table 31-12); it is always enabled.
The second timer is the Oscillator Start-up Timer
(OST), intended to keep the chip in Reset until the
crystal oscillator is stable (HS, XT or LP modes). The
OST does this by counting 1,024 oscillator cycles
before allowing the oscillator to clock the device.
There is a delay of interval, TCSD (parameter 38,
Table 31-12), following POR, while the controller
becomes ready to execute instructions.
TABLE 3-4: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Oscillator Mode
OSC1 Pin
OSC2 Pin
EC, ECPLL
HS, HSPLL
INTOSC, INTPLL1/2
Floating, pulled by external clock
Feedback inverter disabled at quiescent
voltage level
I/O pin, RA6, direction controlled by
TRISA<6>
At logic low (clock/4 output)
Feedback inverter disabled at quiescent
voltage level
I/O pin, RA6, direction controlled by
TRISA<7>
Note: See Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset.
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 53