PIC18F87K22 Datasheet, PDF (157/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
REGISTER 11-18: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3
R/W-1
U-0
TMR5GIP
—
bit 7
R-1
RC2IP
R-1
TX2IP
R/W-1
CTMUIP
R/W-1
CCP2IP
R/W-1
CCP1IP
R/W-1
RTCCIP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
TMR5GIP: Timer5 Gate interrupt Priority bit
1 = High priority
0 = Low priority
bit 6
Unimplemented: Read as ‘0’
bit 5
RC2IP: EUSART Receive Priority Flag bit
1 = High priority
0 = Low priority
bit 4
TX2IP: EUSART Transmit Interrupt Priority bit
1 = High priority
0 = Low priority
bit 3
CTMUIP: CTMU Interrupt Priority bit
1 = High priority
0 = Low priority
bit 2
CCP2IP: ECCP2 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 1
CCP1IP: ECCP1 Interrupt Priority bit
1 = High priority
0 = Low priority
bit 0
RTCCIP: RTCC Interrupt Priority bit
1 = High priority
0 = Low priority
REGISTER 11-19: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4
R/W-1
CCP10IP⁽¹⁾
bit 7
R/W-1
CCP9IP⁽¹⁾
R/W-1
CCP8IP
R/W-1
CCP7IP
R/W-1
CCP6IP
R/W-1
CCP5IP
R/W-1
CCP4IP
R/W-1
CCP3IP
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
CCP<10:3>IP: CCP<10:3> Interrupt Priority bit⁽¹⁾
1 = High priority
0 = Low priority
Note 1: CCP10IP and CCP9IP are unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 157