PIC18F87K22 Datasheet, PDF (318/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
21.4.12 ACKNOWLEDGE SEQUENCE
TIMING
An Acknowledge sequence is enabled by setting the
Acknowledge Sequence Enable bit, ACKEN
(SSPxCON2<4>). When this bit is set, the SCLx pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDAx pin. If the user wishes to gen-
erate an Acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The Baud Rate Gen-
erator then counts for one rollover period (TBRG) and the
SCLx pin is deasserted (pulled high). When the SCLx pin
is sampled high (clock arbitration), the Baud Rate Gener-
ator counts for TBRG; the SCLx pin is then pulled low.
Following this, the ACKEN bit is automatically cleared, the
Baud Rate Generator is turned off and the MSSP module
then goes into an inactive state (Figure 21-25).
21.4.12.1 WCOL Status Flag
If the user writes the SSPxBUF when an Acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
21.4.13 STOP CONDITION TIMING
A Stop bit is asserted on the SDAx pin at the end of a
receive/transmit by setting the Stop Sequence Enable
bit, PEN (SSPxCON2<2>). At the end of a
receive/transmit, the SCLx line is held low after the
falling edge of the ninth clock. When the PEN bit is set,
the master will assert the SDAx line low. When the
SDAx line is sampled low, the Baud Rate Generator is
reloaded and counts down to 0. When the Baud Rate
Generator times out, the SCLx pin will be brought high
and one TBRG (Baud Rate Generator rollover count)
later, the SDAx pin will be deasserted. When the SDAx
pin is sampled high while SCLx is high, the P bit
(SSPxSTAT<4>) is set. A TBRG later, the PEN bit is
cleared and the SSPxIF bit is set (Figure 21-26).
21.4.13.1 WCOL Status Flag
If the user writes the SSPxBUF when a Stop sequence
is in progress, then the WCOL bit is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 21-25: ACKNOWLEDGE SEQUENCE WAVEFORM
Acknowledge Sequence Starts Here,
Write to SSPxCON2,
ACKEN = 1, ACKDT = 0
TBRG
TBRG
SDAx
D0
ACK
ACKEN Automatically Cleared
SCLx
8
9
SSPxIF
SSPxIF Set at
the End of Receive
Cleared in
Software
Note: TBRG = one Baud Rate Generator period.
Cleared in
Software
SSPxIF Set at the End
of Acknowledge Sequence
FIGURE 21-26: STOP CONDITION RECEIVE OR TRANSMIT MODE
Write to SSPxCON2,
Set PEN
Falling Edge of
9th Clock
SCLx
TBRG
SCLx = 1 for TBRG, Followed by SDAx = 1 for TBRG
after SDAx Sampled High. P bit (SSPxSTAT<4>) is Set
PEN bit (SSPxCON2<2>) is Cleared by
Hardware and the SSPxIF bit is Set
SDAx
ACK
TBRG
TBRG
P
TBRG
SCLx Brought High After TBRG
SDAx Asserted Low Before Rising Edge of Clock
to Set up Stop Condition
Note: TBRG = one Baud Rate Generator period.
DS39960B-page 318
Preliminary
 2010 Microchip Technology Inc.