PIC18F87K22 Datasheet, PDF (98/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Address File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
FB6h PIE4
CCP10IE⁽³⁾ CCP9IE⁽³⁾ CCP8IE
CCP7IE
CCP6IE
CCP5IE
CCP4IE
FB5h CVRCON
CVREN
CVROE
CVRSS
CVR4
CVR3
CVR2
CVR1
FB4h CMSTAT
CMP3OUT CMP2OUT CMP1OUT
—
—
—
—
FB3h TMR3H
Timer3 Register High Byte
FB2h TMR3L
Timer3 Register Low Byte
FB1h T3CON
TMR3CS1 TMR3CS0 T3CKPS1 T3CKPS0 SOSCEN T3SYNC
RD16
FB0h T3GCON
TMR3GE T3GPOL
T3GTM
T3GSPM
T3GGO/
T3DONE
T3GVAL
T3GSS1
FAFh SPBRG1
USART1 Baud Rate Generator
FAEh RCREG1
USART1 Receive Register
FADh TXREG1
USART1 Transmit Register
FACh TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
FABh RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
FAAh T1GCON
TMR1GE T1GPOL
T1GTM
T1GSPM
T1GGO/
T1DONE
T1GVAL
T1GSS1
FA9h IPR6
—
—
—
EEIP
—
CMP3IP
CMP2IP
FA8h HLVDCON
VDIRMAG BGVST
IRVST
HLVDEN
HLVDL3
HLVDL2
HLVDL1
FA7h PSPCON
IBF
OBF
IBOV
PSPMODE
—
—
—
FA6h PIR6
—
—
—
EEIF
—
CMP3IF
CMP2IF
FA5h IPR3
TMR5GIP
—
RC2IP
TX2IP
CTMUIP
CCP2IP
CCP1IP
FA4h PIR3
TMR5GiF
—
RC2IF
TX2IF
CTMUIF
CCP2IF
CCP1IF
FA3h PIE3
TMR5GIE
—
RC2IE
TX2IE
CTMUIE
CCP2IE
CCP1IE
FA2h IPR2
OSCFIP
—
SSP2IP
BCL2IP
BCL1IP
HLVDIP
TMR3IP
FA1h PIR2
OSCFIF
—
SSP2IF
BCL2IF
BCL1IF
HLVDIF
TMR3IF
FA0h PIE2
OSCFIE
—
SSP2IE
BCL2IE
BCL1IE
HLVDIE
TMR3IE
F9Fh IPR1
PSPIP
ADIP
RC1IP
TX1IP
SSP1IP TMR1GIP TMR2IP
F9Eh PIR1
PSPIF
ADIF
RC1IF
TX1IF
SSP1IF TMR1GIF TMR2IF
F9Dh PIE1
PSPIE
ADIE
RC1IE
TX1IE
SSP1IE TMR1GIE TMR2IE
F9Ch PSTR1CON
CMPL1
CMPL0
—
STRSYNC STRD
STRC
STRB
F9Bh
F9Ah
F99h
OSCTUNE
TRISJ⁽²⁾
TRISH⁽²⁾
INTSRC
TRISJ7
TRISH7
PLLEN
TRISJ6
TRISH6
TUN5
TRISJ5
TRISH5
TUN4
TRISJ4
TRISH4
TUN3
TRISJ3
TRISH3
TUN2
TRISJ2
TRISH2
TUN1
TRISJ1
TRISH1
F98h TRISG
—
—
—
TRISG4
TRISG3
TRISG2
TRISG1
F97h TRISF
TRISF7
TRISF6
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
F96h TRISE
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
F95h TRISD
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
F94h TRISC
TRISC7
TRISC6
TRISC5
TRISC4
TRISC3
TRISC2
TRISC1
F93h TRISB
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
F92h
F91h
F90h
TRISA
LATJ⁽²⁾
LATH⁽²⁾
TRISA7
LATJ7
LATH7
TRISA6
LATJ6
LATH6
TRISA5
LATJ5
LATH5
TRISA4
LATJ4
LATH4
TRISA3
LATJ3
LATH3
TRISA2
LATJ2
LATH2
TRISA1
LATJ1
LATH1
F8Fh LATG
—
—
—
LATG4
LATG3
LATG2
LATG1
F8Eh LATF
LATF7
LATF6
LATF5
LATF4
LATF3
LATF2
LATF1
F8Dh LATE
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
F8Ch LATD
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
F8Bh LATC
LATC7
LATC6
LATC5
LATC4
LATC3
LATC2
LATC1
F8Ah LATB
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
F89h
F88h
F87h
LATA
PORTJ⁽²⁾
PORTH⁽²⁾
LATA7
RJ7
RH7
LATA6
RJ6
RH6
LATA5
RJ5
RH5
LATA4
RJ4
RH4
LATA3
RJ3
RH3
LATA2
RJ2
RH2
LATA1
RJ1
RH1
Note 1:
2:
3:
The bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
Unimplemented on 64-pin devices (PIC18F6XK22).
Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
Bit 0
CCP3IE
CVR0
—
TMR3ON
T3GSS0
TX9D
RX9D
T1GSS0
CMP1IP
HLVDL0
—
CMP1IF
RTCCIP
RTCCIF
RTCCIE
TMR3GIP
TMR3GIF
TMR3GIE
TMR1IP
TMR1IF
TMR1IE
STRA
TUN0
TRISJ0
TRISH0
TRISG0
—
—
TRISD0
TRISC0
TRISB0
TRISA0
LATJ0
LATH0
LATG0
—
LATE0
LATD0
LATC0
LATB0
LATA0
RJ0
RH0
Value on
POR, BOR
0000 0000
0000 0000
xxx- ----
xxxx xxxx
xxxx xxxx
0000 0000
0000 0x00
0000 0000
0000 0000
xxxx xxxx
0000 0010
0000 000x
0000 0x00
---0 -000
0000 0000
0000 ----
---0 -000
1-11 1111
0-00 0000
0-00 0000
1-11 1110
0-10 0000
0-10 0000
1111 1111
0000 0000
0000 0000
00-0 0001
0000 0000
1111 1111
1111 1111
---1 1111
1111 111-
1111 111-
1111 1111
1111 1111
1111 1111
1111 1111
xxxx xxxx
xxxx xxxx
---x xxxx
xxxx xxx-
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
DS39960B-page 98
Preliminary
 2010 Microchip Technology Inc.