PIC18F87K22 Datasheet, PDF (96/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
TABLE 6-1: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87K22 FAMILY (CONTINUED)
Addr.
Name
F3Fh
F3Eh
F3Dh
F3Ch
TMR7H⁽⁴⁾
TMR7L⁽⁴⁾
T7CON⁽⁴⁾
T7GCON⁽⁴⁾
F3Bh TMR6
F3Ah
PR6
F39H T6CON
F38h TMR8
F37h
PR8
F36h
F35h
F34h
F33h
T8CON
TMR10⁽⁴⁾
PR10⁽⁴⁾
T10CON⁽⁴⁾
Addr.
Name
Addr.
Name
Addr.
F32h
F31h
F30h
TMR12⁽⁴⁾
PR12⁽⁴⁾
T12CON⁽⁴⁾
F25h
F24h
F23h
ANCON0
ANCON1
ANCON2
F18h
F17h
F16h
F2Fh CM2CON F22h RCSTA2
F2Eh CM3CON F21h TXSTA2
F2Dh CCPTMRS0 F20h BAUDCON2
F2Ch CCPTMRS1 F1Fh SPBRGH2
F2Bh CCPTMRS2 F1Eh SPBRG2
F2Ah REFOCON F1Dh RCREG2
F29H ODCON1 F1Ch TXREG2
F28h ODCON2 F1Bh PSTR2CON
F27h ODCON3 F1Ah PSTR3CON
F26h MEMCON F19h PMD0
Name
PMD1
PMD2
PMD3
Addr.
Name
Addr.
Name
Note 1:
2:
3:
4:
5:
This is not a physical register.
Unimplemented registers are read as ‘0’.
This register is not available on 64-pin devices (PIC18F6XK22).
This register is not available on devices with a program memory of 32 Kbytes (PIC18FX5K22).
Addresses, F16h through F5Fh, are also used by SFRs, but are not part of the Access RAM. To access these registers,
users must always load the proper BSR value.
TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY
Address File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
FFFh TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
FFEh TOSH
Top-of-Stack High Byte (TOS<15:8>)
FFDh TOSL
Top-of-Stack Low Byte (TOS<7:0>)
FFCh STKPTR
STKFUL STKUNF
—
Return Stack Pointer
FFBh PCLATU
—
—
—
Holding Register for PC<20:16>
FFAh PCLATH
Holding Register for PC<15:8>
FF9h PCL
PC Low Byte (PC<7:0>)
FF8h TBLPTRU
—
—
bit 21 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
FF7h TBLPTRH
Program Memory Table Pointer High Byte (TBLPTR<15:8>)
FF6h TBLPTRL
Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
FF5h TABLAT
Program Memory Table Latch
FF4h
FF3h
PRODH
PRODL
Product Register High Byte
Product Register Low Byte
FF2h INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
FF1h INTCON2
RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP
INT3IP
RBIP
FF0h INTCON3
INT2IP
INT1IP
INT3IE
INT2IE
INT1IE
INT3IF
INT2IF
INT1IF
FEFh INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
FEEh POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
FEDh POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
FECh PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
FEBh PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value
of FSR0 offset by W
FEAh FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High
FE9h FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
FE8h WREG
Working Register
FE7h INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
Note 1:
2:
3:
The bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
Unimplemented on 64-pin devices (PIC18F6XK22).
Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
---0 0000
0000 0000
0000 0000
uu-0 0000
---0 0000
0000 0000
0000 0000
--00 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 000x
1111 1111
1100 0000
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xxxx xxxx
xxxx xxxx
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DS39960B-page 96
Preliminary
 2010 Microchip Technology Inc.