PIC18F87K22 Datasheet, PDF (178/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
TABLE 12-9: PORTE FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RE7/ECCP2/
RE7
0
P2A/AD15
1
ECCP2⁽¹⁾
0
O
DIG LATE<7> data output.
I
ST PORTE<7> data input.
O
DIG ECCP2 compare/PWM output; takes priority over port data.
1
I
ST ECCP2 Capture input.
P2A
0
O
— ECCP2 PWM Output A.
May be configured for tri-state during Enhanced PWM shutdown event.
AD15
x
O
DIG External memory interface, Address/Data Bit 15 output.
x
I
TTL External memory interface, Data Bit 15 input.
Legend:
Note 1:
2:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Microcontroller mode.
This feature is only available on PIC18F8XKXX devices.
TABLE 12-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTE
RE7
RE6
RE5
RE4
RE3
LATE
LATE7
LATE6
LATE5 LATE4 LATE3
TRISE
TRISE7
TRISE6 TRISE5 TRISE4 TRISE3
PADCFG1
RDPU
REPU
—
—
—
ODCON1 SSP1OD CCP2OD CCP1OD
—
—
ODCON2 CCP10OD⁽¹⁾ CCP9OD⁽¹⁾ CCP8OD CCP7OD CCP6OD
Legend: Shaded cells are not used by PORTE.
Note 1: Unimplemented on PIC18FX5K22 devices, read as ‘0’.
RE2
RE1
RE0
LATE2
LATE1
LATE0
TRISE2
TRISE1 TRISE0
RTSECSEL1 RTSECSEL0 —
—
—
SSP2OD
CCP5OD CCP4OD CCP3OD
DS39960B-page 178
Preliminary
 2010 Microchip Technology Inc.