PIC18F87K22 Datasheet, PDF (135/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

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9.6 Operation During Code-Protect
Data EEPROM memory has its own code-protect bits in
Configuration Words. External read and write
operations are disabled if code protection is enabled.
The microcontroller itself can both read and write to the
internal data EEPROM, regardless of the state of the
code-protect Configuration bit. Refer to Section 28.0
“Special Features of the CPU” for additional
information.
9.7 Protection Against Spurious Write
There are conditions when the device may not want to
write to the data EEPROM memory. To protect against
spurious EEPROM writes, various mechanisms have
been implemented. On power-up, the WREN bit is
cleared. In addition, writes to the EEPROM are blocked
during the Power-up Timer period (TPWRT,
parameter 33).
The write initiate sequence, and the WREN bit
together, help prevent an accidental write during
brown-out, power glitch or software malfunction.
9.8 Using the Data EEPROM
The data EEPROM is a high-endurance, byte address-
able array that has been optimized for the storage of
frequently changing information (e.g., program
variables or other data that is updated often).
Frequently changing values will typically be updated
more often than specification, D124. If this is not the
case, an array refresh must be performed. For this
reason, variables that change infrequently (such as
constants, IDs, calibration, etc.) should be stored in
Flash program memory.
A simple data EEPROM refresh routine is shown in
Example 9-3.
Note:
If data EEPROM is only used to store
constants and/or data that changes often,
an array refresh is likely not required. See
specification, D124.
EXAMPLE 9-3: DATA EEPROM REFRESH ROUTINE
LOOP
CLRF
CLRF
BCF
BCF
BCF
BSF
EEADR
EEADRH
EECON1, CFGS
EECON1, EEPGD
INTCON, GIE
EECON1, WREN
BSF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BTFSC
BRA
INCFSZ
BRA
INCFSZ
BRA
EECON1, RD
0x55
EECON2
0xAA
EECON2
EECON1, WR
EECON1, WR
$-2
EEADR, F
LOOP
EEADRH, F
LOOP
; Start at address 0
;
; Set for memory
; Set for Data EEPROM
; Disable interrupts
; Enable writes
; Loop to refresh array
; Read current address
;
; Write 55h
;
; Write 0AAh
; Set WR bit to begin write
; Wait for write to complete
; Increment address
; Not zero, do it again
; Increment the high address
; Not zero, do it again
BCF
EECON1, WREN
BSF
INTCON, GIE
; Disable writes
; Enable interrupts
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 135