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PIC18F87K22 Datasheet, PDF (443/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology | |||
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PIC18F87K22 FAMILY
BTG
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Bit Toggle f
BTG f, b {,a}
0 ï£ f ï£ 255
0ï£b<7
a ïï [0,1]
(f<b>) ï® f<b>
None
0111 bbba ffff ffff
Bit âbâ in data memory location, âfâ, is
inverted.
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank.
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ï£ï 95 (5Fh). See
Section 29.2.3 âByte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Modeâ for details.
1
1
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write
register âfâ
Example:
BTG
PORTC, 4, 0
Before Instruction:
PORTC =
After Instruction:
PORTC =
0111 0101 [75h]
0110 0101 [65h]
BOV
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If Jump:
Q1
Decode
No
operation
If No Jump:
Q1
Decode
Branch if Overflow
BOV n
-128 ï£ n ï£ 127
if Overflow bit is â1â,
(PC) + 2 + 2n ï® PC
None
1110 0100 nnnn nnnn
If the Overflow bit is â1â, then the
program will branch.
The 2âs complement number â2nâ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
Q2
Read literal
ânâ
No
operation
Q3
Process
Data
No
operation
Q4
Write to PC
No
operation
Q2
Read literal
ânâ
Q3
Process
Data
Q4
No
operation
Example:
HERE
Before Instruction
PC
=
After Instruction
If Overflow =
PC
=
If Overflow =
PC
=
BOV Jump
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
ï£ 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 443
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