PIC18F87K22 Datasheet, PDF (466/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
SUBWFB
Subtract W from f with Borrow
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
SUBWFB f {,d {,a}}
0  f  255
d  [0,1]
a  [0,1]
(f) – (W) – (C) dest
N, OV, C, DC, Z
0101 10da ffff ffff
Subtract W and the Carry flag (borrow)
from register ‘f’ (2’s complement
method). If ‘d’ is ‘0’, the result is stored
in W. If ‘d’ is ‘1’, the result is stored back
in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example 1:
SUBWFB
Before Instruction
REG = 19h
W
= 0Dh
C
=1
After Instruction
REG
W
C
Z
N
= 0Ch
= 0Dh
=1
=0
=0
Example 2:
SUBWFB
Before Instruction
REG
W
C
= 1Bh
= 1Ah
=0
After Instruction
REG
W
= 1Bh
= 00h
C
=1
Z
=1
N
=0
Example 3:
SUBWFB
Before Instruction
REG
W
C
= 03h
= 0Eh
=1
After Instruction
REG = F5h
W
= 0Eh
C
=0
Z
=0
N
=1
REG, 1, 0
(0001 1001)
(0000 1101)
(0000 1011)
(0000 1101)
; result is positive
REG, 0, 0
(0001 1011)
(0001 1010)
(0001 1011)
; result is zero
REG, 1, 0
(0000 0011)
(0000 1101)
(1111 0100)
; [2’s comp]
(0000 1101)
; result is negative
SWAPF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Swap f
SWAPF f {,d {,a}}
0  f  255
d  [0,1]
a  [0,1]
(f<3:0>)  dest<7:4>,
(f<7:4>)  dest<3:0>
None
0011 10da ffff ffff
The upper and lower nibbles of register
‘f’ are exchanged. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
placed in register ‘f’.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Q2
Read
register ‘f’
Q3
Process
Data
Q4
Write to
destination
Example:
SWAPF
Before Instruction
REG = 53h
After Instruction
REG = 35h
REG, 1, 0
DS39960B-page 466
Preliminary
 2010 Microchip Technology Inc.