PIC18F87K22 Datasheet, PDF (176/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
12.6 PORTE, TRISE and
LATE Registers
PORTE is a eight-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISE and LATE.
All pins on PORTE are implemented with Schmitt
Trigger input buffers. Each pin is individually
configurable as an input or output. The RE7 pin is also
configurable for open-drain output when ECCP2 is
active on this pin. Open-drain configuration is selected
by setting the CCP2OD control bit (ODCON1<6>)
Note: These pins are configured as digital inputs
on any device Reset.
Each of the PORTE pins has a weak internal pull-up. A
single control bit can turn off all the pull-ups. This is
performed by setting bit, REPU (PADCFG1<6>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on any device Reset.
PORTE is also multiplexed with Enhanced PWM Out-
puts B and C, for ECCP1 and ECCP3, and Outputs B,
C and D, for ECCP2. For all devices, their default
assignments are on PORTE<6:0>.
On 80-pin devices, the multiplexing for the outputs of
ECCP1 and ECCP3 is controlled by the ECCPMX Con-
figuration bit. Clearing this bit reassigns the P1B/P1C
and P3B/P3C outputs to PORTH.
For devices operating in Microcontroller mode, pin, RE7,
can be configured as the alternate peripheral pin for the
ECCP2 module and Enhanced PWM Output 2A. This is
done by clearing the CCP2MX Configuration bit. PORTE
is also multiplexed with the Parallel Slave Port address
lines. RE1 and RE0 are multiplexed with the control
signals, WR and RD.
RE3 can also be configured as the Reference Clock
Output (REFO) from the system clock. For further
details, see Section 3.7 “Reference Clock Output”.
EXAMPLE 12-5: INITIALIZING PORTE
CLRF
CLRF
MOVLW
MOVWF
PORTE
LATE
03h
TRISE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE<1:0> as inputs
; RE<7:2> as outputs
TABLE 12-9: PORTE FUNCTIONS
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RE0/P2D/RD/
RE0
AD8
0
O
DIG LATE<0> data output.
1
I
ST PORTE<0> data input.
P2D
0
O
— ECCP2 PWM Output D.
May be configured for tri-state during Enhanced PWM shutdown events.
RD
AD8⁽²⁾
x
O
DIG Parallel Slave Port read strobe pin.
x
I
TTL Parallel Slave Port read pin.
x
O
DIG External memory interface, Data Bit 8 output.
x
I
TTL External memory interface, Data Bit 8 input.
RE1/P2C/WR/
RE1
AD9
0
O
DIG LATE<1> data output.
1
I
ST PORTE<1> data input.
P2C
0
O
— ECCP2 PWM Output C.
May be configured for tri-state during Enhanced PWM shutdown events.
WR
x
O
DIG Parallel Slave Port write strobe pin.
x
I
TTL Parallel Slave Port write pin.
AD9
x
O
DIG External memory interface, Data Bit 9 output.
x
I
TTL External memory interface, Data Bit 9 input.
Legend:
Note 1:
2:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Microcontroller mode.
This feature is only available on PIC18F8XKXX devices.
DS39960B-page 176
Preliminary
 2010 Microchip Technology Inc.