PIC18F87K22 Datasheet, PDF (69/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
TABLE 4-4:
EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Power-Managed
Mode
Clock Source⁽⁵⁾
Exit Delay
Clock Ready
Status Bits
LP, XT, HS
HSPLL
OSTS
PRI_IDLE mode
EC, RC
HF-INTOSC⁽²⁾
MF-INTOSC⁽²⁾
TCSD⁽¹⁾
HFIOFS
MFIOFS
SEC_IDLE mode
RC_IDLE mode
LF-INTOSC
SOSC
HF-INTOSC⁽²⁾
MF-INTOSC⁽²⁾
TCSD⁽¹⁾
TCSD⁽¹⁾
None
SOSCRUN
HFIOFS
MFIOFS
Sleep mode
LF-INTOSC
LP, XT, HS
HSPLL
EC, RC
HF-INTOSC⁽²⁾
MF-INTOSC⁽²⁾
TOST⁽³⁾
TOST + t_rc⁽³⁾
TCSD⁽¹⁾
TIOBST⁽⁴⁾
None
OSTS
HFIOFS
MFIOFS
LF-INTOSC
None
Note 1: TCSD (parameter 38, Table 31-12) is a required delay when waking from Sleep and all Idle modes, and
runs concurrently with any other required delays (see Section 4.4 “Idle Modes”).
2: Includes postscaler derived frequencies. On Reset, INTOSC defaults to HF-INTOSC at 8 MHz.
3: TOST is the Oscillator Start-up Timer (parameter 32, Table 31-12). TRC is the PLL Lock-out Timer
(parameter F12, Table 31-7); it is also designated as TPLL.
4: Execution continues during TIOBST (parameter 39, Table 31-12), the INTOSC stabilization period.
5: The clock source is dependent upon the settings of the SCS (OSCCON<1:0>), IRCF (OSCCON<6:4>)
and FOSC (CONFIG1H<3:0>) bits.
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 69