PIC18F87K22 Datasheet, PDF (177/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
TABLE 12-9: PORTE FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RE2/P2B/
CCP10/CS/
AD10
RE2
0
O
DIG LATE<2> data output.
1
I
ST PORTE<2> data input.
P2B
0
O
— ECCP2 PWM Output B.
May be configured for tri-state during Enhanced PWM shutdown events.
CCP10
1
I/O
ST Capture 10 input/Compare 10 output/PWM10 output.
CS
x
I
TTL Parallel Slave Port chip select.
AD10
x
O
DIG External memory interface, Address/Data Bit 10 output.
x
I
TTL External memory interface, Data Bit 10 input.
RE3/P3C/
RE3
CCP9/REFO/
AD11
P3C
0
O
DIG LATE<3> data output.
1
I
ST PORTE<3> data input.
0
O
— ECCP3 PWM Output C.
May be configured for tri-state during Enhanced PWM shutdown events.
CCP9
0
O
DIG CCP9 Compare/PWM output. Takes priority over port data.
1
I
ST CCP9 capture input.
REFO
x
O
DIG Reference output clock.
AD11
x
O
DIG External memory interface, Address/Data Bit 11 output.
x
I
TTL External memory interface, Data Bit 11 input.
RE4/P3B/
RE4
0
O
DIG LATE<4> data output.
CCP8/AD12
1
I
ST PORTE<4> data input.
P3B
0
O
— ECCP3 PWM Output B.
May be configured for tri-state during Enhanced PWM shutdown events.
CCP8
0
O
DIG CCP8 compare/PWM output. Takes priority over port data.
1
I
ST CCP8 capture input.
AD12
x
O
DIG External memory interface, Address/Data Bit 12 output.
x
I
TTL External memory interface, Data Bit 12 input.
RE5/P1C/
RE5
0
O
DIG LATE<5> data output.
CCP7/AD13
1
I
ST PORTE<5> data input.
P1C
0
O
— ECCP1 PWM Output C.
May be configured for tri-state during Enhanced PWM shutdown events.
CCP7
0
O
DIG CCP7 compare/PWM output. Takes priority over port data.
1
I
ST CCP7 capture input.
AD13
x
O
DIG External memory interface, Address/Data Bit 13 output.
x
I
TTL External memory interface, Data bit 13 input.
RE6/P1B/
RE6
0
O
DIG LATE<6> data output.
CCP6/AD14
1
I
ST PORTE<6> data input.
P1B
0
O
— ECCP1 PWM Output B.
May be configured for tri-state during Enhanced PWM shutdown events.
CCP6
0
O
DIG CCP6 compare/PWM output. Takes priority over port data.
1
I
ST CCP9 capture input.
AD14
x
O
DIG External memory interface, Address/Data Bit 14 output.
x
I
TTL External memory interface, Data Bit 14 input.
Legend:
Note 1:
2:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared and in Microcontroller mode.
This feature is only available on PIC18F8XKXX devices.
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 177