PIC18F87K22 Datasheet, PDF (451/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
INCFSZ
Increment f, Skip if 0
Syntax:
INCFSZ f {,d {,a}}
Operands:
Operation:
Status Affected:
Encoding:
Description:
0  f  255
d  [0,1]
a  [0,1]
(f) + 1  dest,
skip if result = 0
None
0011 11da ffff ffff
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
Words:
1
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register ‘f’
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
Write to
destination
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
NZERO
ZERO
INCFSZ
:
:
CNT, 1, 0
Before Instruction
PC
=
After Instruction
CNT =
If CNT =
PC
=
If CNT 
PC
=
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
INFSNZ
Increment f, Skip if Not 0
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
INFSNZ f {,d {,a}}
0  f  255
d  [0,1]
a  [0,1]
(f) + 1  dest,
skip if result  0
None
0100 10da ffff ffff
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’.
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
Words:
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 29.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Decode
Read
register ‘f’
Process
Data
If skip:
Q1
Q2
Q3
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Q4
Write to
destination
Q4
No
operation
Q4
No
operation
No
operation
Example:
HERE
ZERO
NZERO
INFSNZ REG, 1, 0
Before Instruction
PC
=
After Instruction
REG =
If REG 
PC
=
If REG =
PC
=
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 451