PIC18F87K22 Datasheet, PDF (353/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

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23.2.2 A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is where the 12-bit
A/D result and extended sign bits (ADSGN) are loaded
at the completion of a conversion. This register pair is
16 bits wide. The A/D module gives the flexibility of left
or right justifying the 12-bit result in the 16-bit result
register. The A/D Format Select bit (ADFM) controls
this justification.
FIGURE 23-3:
A/D RESULT JUSTIFICATION
Figure 23-3 shows the operation of the A/D result justi-
fication and location of the extended sign bits
(ADSGN). The extended sign bits allow for easier
16-bit math to be performed on the result.
When the A/D Converter is disabled, these 8-bit
registers can be used as two, general purpose registers.
Left Justified
ADFM = 0
12-Bit Result
Right Justified
ADFM = 1
ADRESH
ADRESL
ADRESH
ADRESL
Result bits
ADSGN bit
REGISTER 23-4: ADRESH: A/D RESULT HIGH BYTE REGISTER, LEFT JUSTIFIED (ADFM = 0)
R/W-x
ADRES11
bit 7
R/W-x
ADRES10
R/W-x
ADRES9
R/W-x
ADRES8
R/W-x
ADRES7
R/W-x
ADRES6
R/W-x
ADRES5
R/W-x
ADRES4
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
ADRES<11:4>: A/D Result High Byte bits
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 353