PIC18F87K22 Datasheet, PDF (192/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
13.1 Timer0 Operation
Timer0 can operate as either a timer or a counter. The
mode is selected with the T0CS bit (T0CON<5>). In
Timer mode (T0CS = 0), the module increments on
every clock by default unless a different prescaler value
is selected (see Section 13.3 “Prescaler”). If the
TMR0 register is written to, the increment is inhibited
for the following two instruction cycles. The user can
work around this by writing an adjusted value to the
TMR0 register.
The Counter mode is selected by setting the T0CS bit
(= 1). In this mode, Timer0 increments either on every
rising edge or falling edge of the T0CKI pin. The
incrementing edge is determined by the Timer0 Source
Edge Select bit, T0SE (T0CON<4>); clearing this bit
selects the rising edge. Restrictions on the external
clock input are discussed below.
An external clock source can be used to drive Timer0;
however, it must meet certain requirements to ensure
that the external clock can be synchronized with the
internal phase clock (TOSC). There is a delay between
synchronization and the onset of incrementing the
timer/counter.
13.2 Timer0 Reads and Writes in 16-Bit
Mode
TMR0H is not the actual high byte of Timer0 in 16-bit
mode. It is actually a buffered version of the real high
byte of Timer0, which is not directly readable nor
writable. (See Figure 13-2.) TMR0H is updated with the
contents of the high byte of Timer0 during a read of
TMR0L. This provides the ability to read all 16 bits of
Timer0 without having to verify that the read of the high
and low byte were valid, due to a rollover between
successive reads of the high and low byte.
Similarly, a write to the high byte of Timer0 must also
take place through the TMR0H Buffer register. The high
byte is updated with the contents of TMR0H when a
write occurs to TMR0L. This allows all 16 bits of Timer0
to be updated at once.
FIGURE 13-1:
TIMER0 BLOCK DIAGRAM (8-BIT MODE)
FOSC/4
0
T0CKI pin
T0SE
1
Sync with
1
Internal
Programmable 0
Clocks
Prescaler
(2 TCY Delay)
T0CS
3
T0PS<2:0>
PSA
TMR0L
8
8
Set
TMR0IF
on Overflow
Internal Data Bus
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
FIGURE 13-2:
TIMER0 BLOCK DIAGRAM (16-BIT MODE)
FOSC/4
0
T0CKI pin
T0SE
T0CS
1
Sync with
1
Internal
Programmable
Prescaler
0
Clocks
(2 TCY Delay)
3
T0PS<2:0>
PSA
TMR0L
8
TMR0
High Byte
8
Set
TMR0IF
on Overflow
8
TMR0H
Read TMR0L
Write TMR0L
8
8
Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
Internal Data Bus
DS39960B-page 192
Preliminary
 2010 Microchip Technology Inc.