PIC18F87K22 Datasheet, PDF (173/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
TABLE 12-5: PORTC FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RC3/SCK1/
SCL1
RC3
0
O DIG LATC<3> data output.
1
I ST PORTC<3> data input.
SCK1
0
O DIG SPI clock output (MSSP module); takes priority over port data.
1
I ST SPI clock input (MSSP module).
SCL1
0
O DIG I²C clock output (MSSP module); takes priority over port data.
1
I
I²C I²C clock input (MSSP module); input type depends on module setting.
RC4/SDI1/
SDA1
RC4
0
O DIG LATC<4> data output.
1
I ST PORTC<4> data input.
SDI1
I ST SPI data input (MSSP module).
SDA1
1
O DIG I²C data output (MSSP module); takes priority over port data.
1
I
I²C I²C data input (MSSP module); input type depends on module setting.
RC5/SDO1
RC5
0
O DIG LATC<5> data output.
1
I ST PORTC<5> data input.
SDO1
0
O DIG SPI data output (MSSP module).
RC6/TX1/CK1 RC6
0
O DIG LATC<6> data output.
1
I ST PORTC<6> data input.
TX1
1
O DIG Synchronous serial data output (EUSART module); takes priority over port data.
CK1
1
O DIG Synchronous serial data input (EUSART module); user must configure as an input.
1
I ST Synchronous serial clock input (EUSART module).
RC7/RX1/DT1 RC7
0
O DIG LATC<7> data output.
1
I ST PORTC<7> data input.
RX1
1
I ST Asynchronous serial receive data input (EUSART module).
DT1
1
O DIG Synchronous serial data output (EUSART module); takes priority over port data.
1
I ST Synchronous serial data input (EUSART module); user must configure as an input.
Legend:
Note 1:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input, TTL = TTL Buffer Input,
I²C = I²C™/SMBus Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
TABLE 12-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
PORTC
RC7
RC6
RC5
LATC
LATC7 LATBC6 LATC5
TRISC
TRISC7 TRISC6 TRISC5
ODCON1
SSP1OD CCP2OD CCP1OD
ODCON3
U2OD
U1OD
—
Legend: Shaded cells are not used by PORTC.
RC4
LATCB4
TRISC4
—
—
RC3
LATC3
TRISC3
—
—
RC2
LATC2
TRISC2
—
—
Bit 1
RC1
LATC1
TRISC1
—
—
Bit 0
RC0
LATC0
TRISC0
SSP2OD
CTMUDS
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 173