PIC18F87K22 Datasheet, PDF (279/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
21.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
21.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D Converters, etc. The MSSP
module can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I²C™)
- Full Master mode
- Slave mode (with general address call)
The I²C interface supports the following modes in
hardware:
• Master mode
• Multi-Master mode
• Slave mode with 5-bit and 7-bit address masking
(with address masking for both 10-bit and 7-bit
addressing)
All members of the PIC18F87K22 family have two
MSSP modules, designated as MSSP1 and MSSP2.
Each module operates independently of the other.
Note:
Throughout this section, generic refer-
ences to an MSSP module in any of its
operating modes may be interpreted as
being equally applicable to MSSP1 or
MSSP2. Register names and module I/O
signals use the generic designator ‘x’ to
indicate the use of a numeral to distinguish
a particular module when required. Control
bit names are not individuated.
21.2 Control Registers
Each MSSP module has three associated control regis-
ters. These include a status register (SSPxSTAT) and
two control registers (SSPxCON1 and SSPxCON2). The
use of these registers and their individual configuration
bits differ significantly depending on whether the MSSP
module is operated in SPI or I²C mode.
Additional details are provided under the individual
sections.
Note:
In devices with more than one MSSP
module, it is very important to pay close
attention to SSPxCON register names.
SSP1CON1 and SSP1CON2 control
different operational aspects of the same
module, while SSP1CON1 and
SSP2CON1 control the same features for
two different modules.
Note:
The SSPxBUF register cannot be used with
read-modify-write instructions, such as
BCF, COMF, etc.
To avoid lost data in Master mode, a read of
the SSPxBUF must be performed to clear
the Buffer Full (BF) detect bit
(SSPSTAT<0>) between each transmission.
21.3 SPI Mode
The SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. All four
modes of SPI are supported. To accomplish
communication, typically three pins are used:
• Serial Data Out (SDOx) – RC5/SDO1 or
RD4/PSP4/SDO2
• Serial Data In (SDIx) – RC4/SDI1/SDA1 or
RD5/PSP5/SDI2/SDA2
• Serial Clock (SCKx) – RC3/SCK1/SCL1 or
RD6/PSP6/SCK2/SCL2
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SSx) – RF7/AN5/SS1 or RD7/SS2
Figure 21-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 21-1:
MSSP BLOCK DIAGRAM
(SPI MODE)
Internal
Data Bus
Read
Write
SSPxBUF reg
SDIx
SDOx
SSPxSR reg
bit 0
Shift
Clock
SSx
SSx Control
Enable
Edge
Select
2
Clock Select
SCKx
SSPM<3:0>
SMP:CKE
2
4
(^TMR22Output )
Edge
Select
Prescaler TOSC
4, 16, 64
Data to TXx/RXx in SSPxSR
TRIS bit
Note:
Only port I/O names are used in this diagram for the
sake of brevity. Refer to the text for a full list of
multiplexed functions.
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 279