PIC18F87K22 Datasheet, PDF (58/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

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If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output (HF-INTOSC/MF-INTOSC) is not
enabled and the HFIOFS and MFIOFS bits will remain
clear. There will be no indication of the current clock
source. The LF-INTOSC source is providing the device
clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output) or if INTSRC or
MFIOSEL is set, the HFIOFS or MFIOFS bit is set after
the INTOSC output becomes stable. For details, see
Table 4-3.
TABLE 4-3:
IRCF<2:0>
000
000
000
Non-Zero
Non-Zero
INTERNAL OSCILLATOR FREQUENCY STABILITY BITS
INTSRC
MFIOSEL
Status of MFIOFS or HFIOFS when INTOSC is Stable
0
x
MFIOFS = 0, HFIOFS = 0 and clock source is LF-INTOSC
1
0
MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC
1
1
MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC
x
0
MFIOFS = 0, HFIOFS = 1 and clock source is HF-INTOSC
x
1
MFIOFS = 1, HFIOFS = 0 and clock source is MF-INTOSC
Clocks to the device continue while the INTOSC source
stabilizes after an interval of TIOBST (parameter 39,
Table 31-12).
If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the HFIOFS or
MFIOFS bit will remain set.
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 4-4). When the clock
switch is complete, the HFIOFS or MFIOFS bit is
cleared, the OSTS bit is set and the primary clock is
providing the device clock. The IDLEN and SCS bits
are not affected by the switch. The LF-INTOSC source
will continue to run if either the WDT or the Fail-Safe
Clock Monitor is enabled.
DS39960B-page 58
Preliminary
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