PIC18F87K22 Datasheet, PDF (60/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
4.3 Sleep Mode
The power-managed Sleep mode in the PIC18F87K22
family of devices is identical to the legacy Sleep mode
offered in all other PIC devices. It is entered by clearing
the IDLEN bit (the default state on device Reset) and
executing the SLEEP instruction. This shuts down the
selected oscillator (Figure 4-5). All clock source status
bits are cleared.
Entering Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the LF-INTOSC source will continue
to operate. If the SOSC oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 4-6). Alternately, the device
will be clocked from the internal oscillator block if either
the Two-Speed Start-up or the Fail-Safe Clock Monitor is
enabled (see Section 28.0 “Special Features of the
CPU”). In either case, the OSTS bit is set when the
primary clock is providing the device clocks. The IDLEN
and SCS bits are not affected by the wake-up.
4.4 Idle Modes
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS<1:0> bits. The CPU,
however, will not be clocked. The clock source status bits
are not affected. This approach is a quick method to
switch from a given Run mode to its corresponding Idle
mode.
If the WDT is selected, the LF-INTOSC source will
continue to operate. If the SOSC oscillator is enabled,
it will also continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of TCSD
(parameter 38, Table 31-12) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or Sleep mode, a WDT time-
out will result in a WDT wake-up to the Run mode
currently specified by the SCS<1:0> bits.
FIGURE 4-5:
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
Q1 Q2 Q3 Q4 Q1
OSC1
CPU
Clock
Peripheral
Clock
Sleep
Program
Counter
PC
PC + 2
FIGURE 4-6:
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
PLL Clock
Output
TOST⁽¹⁾
TPLL⁽¹⁾
CPU Clock
Peripheral
Clock
Program
Counter
PC
PC + 2
Wake Event
OSTS bit Set
Note 1:TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.
PC + 4
PC + 6
DS39960B-page 60
Preliminary
 2010 Microchip Technology Inc.