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PIC18F87K22 Datasheet, PDF (453/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology | |||
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PIC18F87K22 FAMILY
LFSR
Load FSR
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Decode
LFSR f, k
0ï£fï£2
0 ï£ k ï£ 4095
k ï® FSRf
None
1110
1111
1110 00ff k11kkk
0000 k7kkk kkkk
The 12-bit literal âkâ is loaded into the
file select register pointed to by âfâ.
2
2
Q2
Read literal
âkâ MSB
Read literal
âkâ LSB
Q3
Process
Data
Process
Data
Q4
Write
literal âkâ
MSB to
FSRfH
Write literal
âkâ to FSRfL
Example:
LFSR 2, 3ABh
After Instruction
FSR2H
FSR2L
= 03h
= ABh
MOVF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Q1
Decode
Move f
MOVF f {,d {,a}}
0 ï£ f ï£ 255
d ï [0,1]
a ï [0,1]
f ï® dest
N, Z
0101 00da ffff ffff
The contents of register âfâ are moved to
a destination dependent upon the
status of âdâ. If âdâ is â0â, the result is
placed in W. If âdâ is â1â, the result is
placed back in register âfâ. Location âfâ
can be anywhere in the
256-byte bank.
If âaâ is â0â, the Access Bank is selected.
If âaâ is â1â, the BSR is used to select the
GPR bank.
If âaâ is â0â and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ï£ï 95 (5Fh). See
Section 29.2.3 âByte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Modeâ for details.
1
1
Q2
Read
register âfâ
Q3
Process
Data
Q4
Write
W
Example:
MOVF
Before Instruction
REG
=
W
=
After Instruction
REG
=
W
=
REG, 0, 0
22h
FFh
22h
22h
ï£ 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 453
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