PIC18F87K22 Datasheet, PDF (293/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
REGISTER 21-6: SSPxCON2: MSSPx CONTROL REGISTER 2 (I²C™ SLAVE MODE)
R/W-0
GCEN
R/W-1
ACKSTAT
R/W-0
ACKDT
R/W-0
ACKEN⁽¹⁾
R/W-0
RCEN⁽¹⁾
R/W-0
PEN⁽¹⁾
R/W-0
RSEN⁽¹⁾
bit 7
R/W-0
SEN⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
GCEN: General Call Enable bit
1 = Enables interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address is disabled
bit 6
ACKSTAT: Acknowledge Status bit
Unused in Slave mode.
bit 5
ACKDT: Acknowledge Data bit (Master Receive mode only)⁽¹⁾
1 = Not Acknowledge
0 = Acknowledge
bit 4
ACKEN: Acknowledge Sequence Enable bit⁽¹⁾
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit.
Automatically cleared by hardware.
0 = Acknowledge sequence is Idle
bit 3
RCEN: Receive Enable bit (Master Receive mode only)⁽¹⁾
1 = Enables Receive mode for I²C™
0 = Receive is Idle
bit 2
PEN: Stop Condition Enable bit⁽¹⁾
1 = Initiates Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition is Idle
bit 1
RSEN: Repeated Start Condition Enable bit⁽¹⁾
1 = Initiates Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition is Idle
bit 0
SEN: Stretch Enable bit⁽¹⁾
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Note 1: If the I²C module is active, this bit may not be set (no spooling) and the SSPxBUF may not be written (or
writes to the SSPxBUF are disabled).
REGISTER 21-7: SSPxMSK: I²C™ SLAVE ADDRESS MASK REGISTER (7-BIT MASKING MODE)⁽¹⁾
R/W-1
MSK7
R/W-1
MSK6
R/W-1
MSK5
R/W-1
MSK4
R/W-1
MSK3
R/W-1
MSK2
R/W-1
MSK1
R/W-1
MSK0⁽²⁾
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-0
MSK<7:0>: Slave Address Mask Select bit
1 = Masking of corresponding bit of SSPxADD is enabled
0 = Masking of corresponding bit of SSPxADD is disabled
Note 1: This register shares the same SFR address as SSPxADD and is only addressable in select MSSPx
operating modes. See Section 21.4.3.4 “7-Bit Address Masking Mode” for more details.
2: MSK0 is not used as a mask bit in 7-bit addressing.
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 293