PIC18F87K22 Datasheet, PDF (424/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
28.6 Program Verification and
Code Protection
The user program memory is divided into four blocks
for the PIC18FX5K22 and PIC18FX6K22 devices and
eight blocks for PIC18FX7K22 devices. One of these is
a boot block of 1 or 2 Kbytes. The remainder of the
memory is divided into blocks on binary boundaries.
Each of the blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPx)
• Write-Protect bit (WRTx)
• External Block Table Read bit (EBTRx)
Figure 28-6 shows the program memory organization for
48, 64, 96 and 128 Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 28-4.
FIGURE 28-6:
CODE-PROTECTED PROGRAM MEMORY FOR THE PIC18F87K22 FAMILY
000000h
Code Memory
01FFFFh
Unimplemented
Read as ‘0’
200000h
Configuration
and ID
Space
Device/Memory Size
PIC18FX7K22
PIC18FX6K22
PIC18FX5K22
BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0 Address
Boot
Block
2 kW
Block 0
6 kW
Boot
Block
Block 0
7 kW
Boot
Block
2 kW
Block 0
6 kW
Boot
Block
Block 0
7 kW
Boot
Block
2 kW
Block 0
2 kW
Block 1
4 kW
Boot 0000h
Block
Block 0 0800h
3 kW _1000h
17FFh
Block 1 1800
4 kW 3FFF
Block 1
8 kW
Block 1
8 kW
Block 1
8 kW
Block 1
8 kW
Block 2
4 kW
Block 3
4 kW
Block 2 4000h
4 kW 5FFFh
Block 3 6000h
4 kW 7FFF
Block 2 Block 2 Block 2 Block 2
8 kW
8 kW
8 kW
8 kW
8000h
BFFFh
Block 3
8 kW
Block 4
8 kW
Block 3
8 kW
Block 4
8 kW
Block 3
8 kW
Block 3
8 kW
C000h
FFFFh
10000h
13FFFh
Block 5 Block 5
8 kW
8 kW
14000h
17FFFh
Block 6 Block 6
8 kW
8 kW
18000h
1BFFFh
Block 7 Block 7
8 kW
8 kW
1C000h
1FFFFh
3FFFFFh
Note 1: Sizes of memory areas are not to scale.
2: Boot block size is determined by the BBSIZ0 bit (CONFIG4L<4>).
DS39960B-page 424
Preliminary
 2010 Microchip Technology Inc.