PIC18F87K22 Datasheet, PDF (408/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
REGISTER 28-6: CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)
R/P-1
U-0
U-0
U-0
R/P-1
U-0
R/P-1
R/P-1
MCLRE
—
—
—
MSSPMSK
—
ECCPMX⁽¹⁾ CCP2MX
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
P = Programmable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
MCLRE: MCLR Pin Enable bit
1 = MCLR pin is enabled; RG5 input pin is disabled
0 = RG5 input pin is enabled; MCLR is disabled
Unimplemented: Read as ‘0’
MSSPMSK: MSSP V3 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode is enabled
0 = 5-Bit Address Masking mode is enabled
Unimplemented: Read as ‘0’
ECCPMX: ECCP MUX bit⁽¹⁾
1=
- Enhanced CCP1 (P1B/P1C) is multiplexed onto RE6 and RE5, CCP6 onto RE6, and
CCP7 onto RE5
- Enhanced CCP3 (P3B/P3C) is multiplexed onto RE4 and RE3, CCP6 onto RE4
and CCP7 onto RE3
0=
- Enhanced CCP1 (P1B/P1C) is multiplexed onto RH7 and RH6, CCP8 onto RH7, and
CCP9 onto RH6
- Enhanced CCP3 (P3B/P3C) is multiplexed onto RH5 and RH4, CCP8 onto RH5
and CCP9 onto RH4
CCP2MX: ECCP2 MUX bit
1 = ECCP2 is multiplexed with RC1
0 = ECCP2 is multiplexed with RB3 in Extended Microcontroller mode; ECCP2 is multiplexed with
RE7 in Microcontroller mode
Note 1: This feature is only available on 80-pin devices.
DS39960B-page 408
Preliminary
 2010 Microchip Technology Inc.