PIC18F87K22 Datasheet, PDF (28/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
TABLE 1-4: PIC18F8XK22 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number _{Pin Buffer}
TQFP ^{Type Type}
Description
PORTD is a bidirectional I/O port.
RD0/CTPLS
RD0
CTPLS
72
I/O ST
Digital I/O.
O ST
CTMU pulse generator output.
RD1/T5CKI/T7G
RD1
T5CKI
T7G
69
I/O ST
Digital I/O.
I
ST
Timer5 clock input.
I
ST
Timer7 external clock gate input.
RD2/PSP2/AD2
RD2
PSP2⁽⁴⁾
AD2
68
I/O ST
Digital I/O.
I/O TTL
Parallel Slave Port data.
I/O TTL
External Memory Address Data 2.
RD3/PSP3/AD3
RD3
PSP3⁽⁴⁾
AD3
67
I/O ST
Digital I/O.
I/O TTL
Parallel Slave Port data.
I/O TTL
External Memory Address Data 3.
RD4/SDO2/PSP4/AD4
RD4
SDO2
PSP4⁽⁴⁾
AD4
66
I/O ST
Digital I/O.
O
—
SPI data out.
I/O TTL
Parallel Slave Port data.
I/O TTL
External Memory Address Data 4.
RD5/SDI2/SDA2/PSP5/
AD5
RD5
SDI2
SDA2
PSP5⁽⁴⁾
AD5
65
I/O ST
I
ST
I/O I²C
I/O TTL
I/O TTL
Digital I/O.
SPI data in.
I²C™ data I/O.
Parallel Slave Port data.
External Memory Address Data 5.
Legend:
TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I = Input
P = Power
I²C = I²C™/SMBus
CMOS
Analog
O
OD
= CMOS compatible input or output
= Analog input
= Output
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for ECCP2 when the CCP2MX Configuration bit is set.
2: Alternate assignment for ECCP2 when the CCP2MX Configuration bit is cleared.
3: Not available on PIC18F65K22 and PIC18F85K22 devices.
4: PSP is available only in Microcontroller mode.
5: The CC6, CCP7, CCP8 and CCP9 pin placement depends on the setting of the ECCPMX Configuration bit
(CONFIG3H<1>).
DS39960B-page 28
Preliminary
 2010 Microchip Technology Inc.