PIC18F87K22 Datasheet, PDF (543/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
Example SPI Slave Mode (CKE = 0) ........................ 513
Example SPI Slave Mode (CKE = 1) ........................ 514
External Clock........................................................... 501
External Memory Bus for SLEEP (Extended
Microcontroller Mode) ............................... 126, 128
External Memory Bus for TBLRD (Extended
Microcontroller Mode) ............................... 126, 128
Fail-Safe Clock Monitor (FSCM) ............................... 423
First Start Bit Timing ................................................. 313
Full-Bridge PWM Output ........................................... 268
Half-Bridge PWM Output .................................. 266, 273
High-Voltage Detect Operation (VDIRMAG = 1)....... 381
HLVD Characteristics................................................ 508
I²C Acknowledge Sequence ..................................... 318
I²C Bus Data ............................................................. 516
I²C Bus Start/Stop Bits.............................................. 515
I²C Master Mode (7 or 10-Bit Transmission) ............ 316
I²C Master Mode (7-Bit Reception)........................... 317
I²C Slave Mode (10-Bit Reception, SEN = 0,
ADMSK = 01001).............................................. 301
I²C Slave Mode (10-Bit Reception, SEN = 0) ........... 302
I²C Slave Mode (10-Bit Reception, SEN = 1) ........... 307
I²C Slave Mode (10-Bit Transmission)...................... 303
I²C Slave Mode (7-bit Reception, SEN = 0,
ADMSK = 01011).............................................. 299
I²C Slave Mode (7-Bit Reception, SEN = 0) ............. 298
I²C Slave Mode (7-Bit Reception, SEN = 1) ............. 306
I²C Slave Mode (7-Bit Transmission)........................ 300
I²C Slave Mode General Call Address Sequence
(7 or 10-Bit Addressing Mode) .......................... 308
I²C Stop Condition Receive or Transmit Mode ......... 318
Low-Voltage Detect Operation (VDIRMAG = 0) ....... 380
MSSP I²C Bus Data.................................................. 517
MSSP I²C Bus Start/Stop Bits .................................. 517
Parallel Slave Port (PSP) Read ................................ 189
Parallel Slave Port (PSP) Write ................................ 188
Program Memory Read............................................. 505
PWM Auto-Shutdown with Auto-Restart
Enabled (PxRSEN = 1) ..................................... 272
PWM Auto-Shutdown with Firmware Restart
(PxRSEN = 0) ................................................... 272
PWM Direction Change ............................................ 269
PWM Direction Change at Near 100%
Duty Cycle ........................................................ 270
PWM Output ............................................................. 253
PWM Output (Active-High)........................................ 264
PWM Output (Active-Low) ........................................ 265
Repeated Start Condition.......................................... 314
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST) and Power-up Timer (PWRT) ...... 507
Send Break Character Sequence ............................. 342
Slave Synchronization .............................................. 285
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 75
SPI Mode (Master Mode).......................................... 284
SPI Mode (Slave Mode, CKE = 0) ............................ 286
SPI Mode (Slave Mode, CKE = 1) ............................ 286
Steering Event at Beginning of Instruction
(STRSYNC = 1) ................................................ 276
Steering Event at End of Instruction
(STRSYNC = 0) ................................................ 276
Synchronous Reception (Master Mode, SREN) ....... 345
Synchronous Transmission....................................... 343
Synchronous Transmission (Through TXEN) ........... 344
Time-out Sequence on Power-up (MCLR Not
Tied to VDD), Case 1 .......................................... 75
Time-out Sequence on Power-up (MCLR Not
Tied to VDD), Case 2 .......................................... 75
Time-out Sequence on Power-up (MCLR
Tied to VDD, VDD Rise TPWRT) ........................... 74
Timer Pulse Generation............................................ 240
Timer0 and Timer1 External Clock ........................... 509
Timer1 Gate Count Enable Mode............................. 202
Timer1 Gate Single Pulse Mode............................... 204
Timer1 Gate Single Pulse/Toggle
Combined Mode ............................................... 205
Timer1 Gate Toggle Mode........................................ 203
Timer3/5/7 Gate Count Enable Mode....................... 215
Timer3/5/7 Gate Single Pulse Mode......................... 217
Timer3/5/7 Gate Single Pulse/Toggle
Combined Mode ............................................... 218
Timer3/5/7 Gate Toggle Mode.................................. 216
Transition for Entry to Idle Mode ................................ 61
Transition for Entry to SEC_RUN Mode ..................... 57
Transition for Entry to Sleep Mode ............................. 60
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ......................................... 421
Transition for Wake from Idle to Run Mode................ 61
Transition for Wake from Sleep (HSPLL) ................... 60
Transition from RC_RUN Mode to
PRI_RUN Mode.................................................. 59
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) ................................... 57
Transition to RC_RUN Mode...................................... 59
Timing Diagrams and Specifications
Capture/Compare/PWM Requirements.................... 510
CLKO and I/O Requirements............................ 503, 505
EUSART Synchronous Receive
Requirements ................................................... 519
EUSART Synchronous Transmission
Requirements ................................................... 519
Example SPI Mode Requirements (Master Mode,
CKE = 0)........................................................... 511
Example SPI Mode Requirements (Master Mode,
CKE = 1)........................................................... 512
Example SPI Mode Requirements (Slave Mode,
CKE = 0)........................................................... 513
Example SPI Slave Mode Requirements
(CKE = 1).......................................................... 514
External Clock Requirements ................................... 501
HLVD Characteristics ............................................... 508
I²C Bus Data Requirements (Slave Mode) ............... 516
I²C Bus Start/Stop Bits Requirements
(Slave Mode) .................................................... 515
Internal RC Accuracy (INTOSC)............................... 502
MSSP I²C Bus Data Requirements .......................... 518
MSSP I²C Bus Start/Stop Bits Requirements........... 517
PLL Clock ................................................................. 502
Program Memory Write Requirements ..................... 506
Reset, Watchdog Timer, Oscillator Start-up
Timer, Power-up Timer and Brown-out
Reset Requirements......................................... 507
Timer0 and Timer1 External
Clock Requirements ......................................... 509
Top-of-Stack Access........................................................... 87
TSTFSZ ............................................................................ 469
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Preliminary
DS39960B-page 543