PIC18F87K22 Datasheet, PDF (166/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
REGISTER 12-3: ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2
R/W-0
CCP10OD⁽¹⁾
bit 7
R/W-0
CCP9OD⁽¹⁾
R/W-0
CCP8OD
R/W-0
CCP7OD
R/W-0
CCP6OD
R/W-0
CCP5OD
R/W-0
CCP4OD
R/W-0
CCP3OD
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
CCP10OD: CCP10 Open-Drain Output Enable bit⁽¹⁾
1 = Open-drain capability enabled
0 = Open-drain capability disabled
bit 6
CCP9OD: CCP9 Open-Drain Output Enable bit⁽¹⁾
1 = Open-drain capability enabled
0 = Open-drain capability disabled
bit 5
CCP8OD: CCP8 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
bit 4
CCP7OD: CCP7 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
bit 3
CCP6OD: CCP6 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
bit 2
CCP5OD: CCP5 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
bit 1
CCP4OD: CCP4 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
bit 0
CCP3OD: ECCP3 Open-Drain Output Enable bit
1 = Open-drain capability enabled
0 = Open-drain capability disabled
Note 1: Not implemented on devices with 32-byte program memory (PIC18FX5K22).
DS39960B-page 166
Preliminary
 2010 Microchip Technology Inc.