PIC18F87K22 Datasheet, PDF (100/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
TABLE 6-2: PIC18F87K22 FAMILY REGISTER FILE SUMMARY (CONTINUED)
Address File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
F5Ch
F5Bh
F5Ah
F59h
F58h
F57h
F56h
F55h
F54h
F53h
F52h
F51h
F50h
F4Fh
F4Eh
F4Dh
F4Ch
F4Bh
F4Ah
F49h
F48h
F47h
F46h
F45h
F44h
F43h
F42h
F41h
F40h
F3Fh
F3Eh
F3Dh
F3Ch
F3Bh
F3Ah
F39h
F38h
F37h
F36h
F35h
F34h
F33h
F32h
F31h
F30h
F2Fh
F2Eh
F2Dh
Note
RTCVALL
RTCC Value Low Register Window Based on RTCPTR<1:0>
ALRMCFG
ALRMEN
CHIME
AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0
ALRMRPT
ARPT7
ARPT6
ARPT5
ARPT4
ARPT3
ARPT2
ARPT1
ARPT0
ALRMVALH Alarm Value High Register Window Based on APTR<1:0>
ALRMVALL Alarm Value Low Register Window Based on APTR<1:0>
CTMUCONH CTMUEN
—
CTMUSIDL TGEN
EDGEN EDGSEQEN IDISSEN
CTTRIG
CTMUCONL EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT
CTMUICONH ITRIM5
ITRIM4
ITRIM3
ITRIM2
ITRIM1
ITRIM0
IRNG1
IRNG0
CM1CON
PADCFG1
CON
RDPU
COE
REPU
CPOL
RJPU⁽²⁾
EVPOL1
—
EVPOL0
CREF
CCH1
—
RTSECSEL1 RTSECSEL0
CCH0
—
ECCP2AS
ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0 PSS2AC1 PSS2AC0 PSS2BD1 PSS2BD0
ECCP2DEL
P2RSEN
P2DC6
P2DC5
P2DC4
P2DC3
P2DC2
P2DC1
P2DC0
CCPR2H
Capture/Compare/PWM Register 2 High Byte
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
CCP2CON
P2M1
P2M0
DC2B1
DC2B0
CCP2M3 CCP2M2 CCP2M1 CCP2M0
ECCP3AS
ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0 PSS3AC1 PSS3AC0 PSS3BD1 PSS3BD0
ECCP3DEL
P3RSEN
P3DC6
P3DC5
P3DC4
P3DC3
P3DC2
P3DC1
P3DC0
CCPR3H
Capture/Compare/PWM Register 3 High Byte
CCPR3L
Capture/Compare/PWM Register 3 Low Byte
CCP3CON
P3M1
P3M0
DC3B1
DC3B0
CCP3M3 CCP3M2 CCP3M1 CCP3M0
CCPR8H
Capture/Compare/PWM Register 8 High Byte
CCPR8L
Capture/Compare/PWM Register 8 Low Byte
CCP8CON
—
—
DC8B1
DC8B0
CCPR9H⁽³⁾ Capture/Compare/PWM Register 9 High Byte
CCPR9L⁽³⁾ Capture/Compare/PWM Register 9 Low Byte
CCP9CON⁽³⁾
—
—
DC9B1
DC9B0
CCPR10H⁽³⁾ Capture/Compare/PWM Register 10 High Byte
CCPR10L⁽³⁾ Capture/Compare/PWM Register 10 Low Byte
CCP10CON⁽³⁾
—
—
DC10B1 DC10B0
TMR7H⁽³⁾
Timer7 Register High Byte
TMR7L⁽³⁾
Timer7 Register Low Byte
CCP8M3 CCP8M2 CCP8M1 CCP8M0
CCP9M3 CCP9M2 CCP9M1 CCP9M0
CCP10M3 CCP10M2 CCP10M1 CCP10M0
T7CON⁽³⁾
T7GCON⁽³⁾
TMR7CS1
TMR7GE
TMR7CS0
T7GPOL
T7CKPS1
T7GTM
T7CKPS0
T7GSPM
SOSCEN
T7GGO/
T7DONE
T7SYNC
T7GVAL
RD16
T7GSS1
TMR7ON
T7GSS0
TMR6
Timer6 Register
PR6
Timer6 Period Register
T6CON
—
T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0
TMR8
Timer8 Register
PR8
Timer8 Period Register
T8CON
TMR1⁽³⁾0
PR10⁽³⁾
T10CON⁽³⁾
TMR12⁽³⁾
PR12⁽³⁾
T12CON⁽³⁾
—
T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0
TMR10 Register
Timer10 Period Register
—
T10OUTPS3 T10OUTPS2 T10OUTPS1 T10OUTPS0
TMR12 Register
Timer12 Period Register
—
T12OUTPS3 T12OUTPS2 T12OUTPS1 T12OUTPS0
TMR8ON
TMR10ON
TMR12ON
T8CKPS1
T10CKPS1
T12CKPS1
T8CKPS0
T10CKPS0
T12CKPS0
CM2CON
CON
COE
CPOL
EVPOL1 EVPOL0
CREF
CCH1
CCH0
CM3CON
CON
COE
CPOL
EVPOL1 EVPOL0
CREF
CCH1
CCH0
CCPTMRS0 C3TSEL1 C3TSEL0 C2TSEL2 C2TSEL1 C2TSEL0 C1TSEL2 C1TSEL1 C1TSEL0
1: The bit is available when Master Clear is disabled (MCLRE = 0). When MCLRE is set, the bit is unimplemented.
2: Unimplemented on 64-pin devices (PIC18F6XK22).
3: Unimplemented on devices with a program memory of 32 Kbytes (PIC18FX5K22).
0000 0000
0000 0000
0000 0000
xxxx xxxx
0000 0000
0-00 0000
0000 0000
0000 0000
0000 0000
000- -00-
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
-000 0000
0000 0000
1111 1111
-000 0000
0000 0000
1111 1111
-000 0000
0000 0000
1111 1111
-000 0000
0001 1111
0001 1111
0000 0000
DS39960B-page 100
Preliminary
 2010 Microchip Technology Inc.