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PIC18F87K22 Datasheet, PDF (175/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology
PIC18F87K22 FAMILY
TABLE 12-7: PORTD FUNCTIONS (CONTINUED)
Pin Name
Function
TRIS
Setting
I/O
I/O
Type
Description
RD3/PSP3/AD3
RD3
0
O
DIG LATD<3> data output.
PSP3(1)
AD3(2)
1
I
ST PORTD<3> data input.
x
I/O TTL Parallel Slave Port data.
x
I/O TTL External Memory Address/Data 3.
RD4/PSP4/
AD4/SDO2
RD4
PSP4(1)
AD4(2)
0
O
DIG LATD<4> data output.
1
I
ST PORTD<4> data input.
x
I/O TTL Parallel Slave Port data.
x
I/O TTL External Memory Address/Data 4.
SDO2
0
P
DOG SPI data output (MSSP module).
RD5/PSP5/
AD5/SDI2/
SDA2
RD5
PSP5(1)
AD5(2)
0
O
DIG LATD<5> data output.
1
I
ST PORTD<5> data input.
x
I/O TTL Parallel Slave Port data.
x
I/O TTL External Memory Address/Data 5.
SDI2
SDA2
1
I
ST SPI data input (MSSP module).
0
O
I2C I2C data input (MSSP module). Input type depends on module setting.
RD6/PSP6/
AD6/SCK2/
SCL2
RD6
PSP6(1)
AD6(2)
0
O
DIG LATD<6> data output.
1
I
ST PORTD<6> data input.
x
I/O TTL Parallel Slave Port data.
x
I/O TTL External Memory Address/Data 6.
SCK2
0
O
DIG SPI clock output (MSSP module). Takes priority over port data.
SCL2
1
I
ST SPI clock input (MSSP module).
0
O
DIG I2C clock output (MSSP module). Takes priority over port data.
1
I
I2C I2C clock input (MSSP module). Input type depends on module
setting.
RD7/PSP7/
AD7/SS2
RD7
0
O
DIG LATD<7> data output.
1
I
ST PORTD<7> data input.
PSP76(1)
x
I/O TTL Parallel Slave Port data.
AD7(2)
x
I/O TTL External Memory Address/Data 7.
SS2
1
I
TTL Slave select input for MSSP module.
Legend:
Note 1:
2:
O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Trigger Buffer Input,
I2C = I2C™/SMBus Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
PSP is available only in Microcontroller mode.
This feature is available only on PIC18F8XK22 devices.
TABLE 12-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PORTD
RD7
RD6
RD5
RD4
RD3
LATD
LATD7
LATD6
LATD5
LATD4
LATD3
TRISD
PADCFG1
TRISD7
RDPU
TRISD6
REPU
TRISD5
RJPU(1)
TRISD4
—
TRISD3
—
ODCON1 SSP1OD CCP2OD CCP1OD
—
—
Legend: Shaded cells are not used by PORTD.
Note 1: Unimplemented on PIC18F6XK22 devices, read as ‘0’.
RD2
LATD2
TRISD2
RTSECSEL1
—
RD1
LATD1
TRISD1
RESECSEL0
—
RD0
LATD0
TRISD0
—
SSP2OD
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 175