PIC18F87K22 Datasheet, PDF (417/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
28.2 Watchdog Timer (WDT)
For the PIC18F87K22 family of devices, the WDT is
driven by the LF-INTOSC source. When the WDT is
enabled, the clock source is also enabled. The nominal
WDT period is 4 ms and has the same stability as the
LF-INTOSC oscillator.
The 4 ms period of the WDT is multiplied by a 16-bit
postscaler. Any output of the WDT postscaler is
selected by a multiplexer, controlled by bits in
Configuration Register 2H. Available periods range
from 4 ms to 4,194 seconds (about one hour). The
WDT and postscaler are cleared when any of the
following events occur: a SLEEP or CLRWDT instruction
is executed, the IRCF bits (OSCCON<6:4>) are
changed or a clock failure has occurred.
FIGURE 28-1:
WDT BLOCK DIAGRAM
WDT enabled,
SWDTEN disabled
WDT controlled with
SWDTEN bit setting
WDT enabled only while
device active, disabled
WDT disabled in hardware,
SWDTEN disabled
The WDT can be operated in one of four modes as
determined by CONFIG2H<WDTEN<1:0> The four
modes are:
• WDT Enabled
• WDT Disabled
• WDT under software control,
SWDTEN (WDTCON<0>)
• WDT
- Enabled during normal operation
- Disabled during Sleep
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and postscaler counts
when executed.
2: Changing the setting of the IRCF bits
(OSCCON<6:4>) clears the WDT and
postscaler counts.
3: When a CLRWDT instruction is executed,
the postscaler count will be cleared.
WDTEN1
WDTEN0
INTRC Source
Change on IRCF bits
CLRWDT
All Device Resets
WDTPS<3:0>
Sleep
Enable WDT
WDT Counter
128
Programmable Postscaler ^Reset
1:1 to 1:1,048,576
4
Wake-up from
Power-Managed
Modes
WDT
Reset
SWDTEN
WDTEN<1:0>
INTRC Source
Enable WDT
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 417