PIC18F87K22 Datasheet, PDF (215/548 Pages) Microchip Technology – 64/80-Pin, High-Performance, 1-Mbit Enhanced Flash Microcontrollers with 12-Bit A/D and nanoWatt XLP Technology

PIC18F87K22 FAMILY
16.5 Timer3/5/7 Gates
Timer3/5/7 can be configured to count freely or the count
can be enabled and disabled using the Timer3/5/7 gate
circuitry. This is also referred to as the Timer3/5/7 gate
count enable.
The Timer3/5/7 gate can also be driven by multiple
selectable sources.
16.5.1 TIMER3/5/7 GATE COUNT ENABLE
The Timerx Gate Enable mode is enabled by setting
the TMRxGE bit (TxGCON<7>). The polarity of the
Timerx Gate Enable mode is configured using the
TxGPOL bit (TxGCON<6>).
When Timerx Gate Enable mode is enabled, Timer3/5/7
will increment on the rising edge of the Timer3/5/7 clock
source. When Timerx Gate Enable mode is disabled, no
incrementing will occur and Timer3/5/7 will hold the
current count. See Figure 16-2 for timing details.
TABLE 16-1: TIMER3/5/7 GATE ENABLE
SELECTIONS
TxCLK^(†)
TxGPOL
(TxGCON<6>)
TxG Pin
Timerx
Operation

0
0 Counts

0
1 Holds Count

1
0 Holds Count

1
1 Counts
† The clock on which TMR3/5/7 is running. For
more information, see TxCLK in Figure 16-1.
FIGURE 16-2:
TMRxGE
TIMER3/5/7 GATE COUNT ENABLE MODE
TxGPOL
TxG_IN
TxCKI
TxGVAL
Timer3/5/7
N
N+1
N+2
N+3
N+4
 2010 Microchip Technology Inc.
Preliminary
DS39960B-page 215