GMS30C2216 Datasheet, PDF (97/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Instruction Set
3-35
trapno indicates one of the traps 0..63.
Note: At the new stack frame, the saved PC is located in L0 and the saved SR is located in
L1; L2..L5 are free for use as required.
A Frame instruction must be executed before executing any other Trap, Call or Software
instruction or before the interrupt-lock flag L is being cleared, otherwise the beginning of
the register part of the stack at the SP could be overwritten without any warning.
3.29 Frame Instruction
A Frame instruction restructures the current stack frame by
• decrementing the frame pointer FP to include (optionally) passed parameters in the local
register addressing range; the first parameter passed is then addressable as L0;
• resetting the frame length FL to the actual number of registers needed for the current
stack frame.
It also restores the reserve number of 10 registers in the register part of the stack to allow
any further Call, Trap or Software instructions and clears the cache mode flag M.
The frame pointer FP is decremented by the value of the Ls-code and the Ld-code is placed
in the frame length FL (FL = 0 is always interpreted as FL = 16). Then the difference
(available number of registers) - (required number of registers + 10) is evaluated and
interpreted as a signed 7-bit integer.
If the difference is not negative, all the registers required plus the reserve of 10 fit into the
register part of the stack; no further action is needed and the Frame instruction is finished.
If the difference is negative, the content of the old stack pointer SP is compared with the
address in the upper stack bound UB. If the value in the SP is equal or higher than the
value in the UB, a temporary flag is set. Then the contents of the number of local registers
equal to the negative difference evaluated are pushed onto the memory part of the stack,
beginning with the content of the local register addressed absolutely by SP(7..2) being
pushed onto the location addressed by the SP. After each memory cycle, the SP is
incremented by four until the difference is eliminated. A trap to Frame Error occurs after
completion of the push operation when the temporary flag is set.
All condition flags remain unchanged.