GMS30C2216 Datasheet, PDF (271/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

Appendix A. Instruction Set Details
Move Double Word
A-99
MOVD
Format:
RR format
15
OP-code
0000 01
10 9
d
87
s
Rd-code
43
0
Rs-code
s = 0: Rs-code encoded G0..G15 for Rs
s = 1: Rs-code encoded L0..L15 for Rs
d = 0: Rd-code encoded G0..G15 for Rd
d = 1: Rd-code encoded L0..L15 for Rd
Notation:
MOVD Rd, Rs
MOVD Rd, 0 (When SR is denoted as a source operand)
Description:
The double-word source operand is copied to the double-word destination register pair and
condition flags are set or cleared accordingly. The high-order word in Rs is copied first.
When the SR is denoted as a source operand, the source operand is supplied as zero
regardless of the content of SR//G2. When the PC is denoted as destination, the Return
instruction RET is executed instead of the Move Double-Word instruction.
Operation:
If Rd does not denote PC and
Rs does not denote SR then
Rd := Rs;
Rdf := Rsf;
Z := Rd//Rsf = 0;
N := Rd(31);
V := Undefined
If Rd does not denote PC and
Rs denotes SR then
Rd := 0;
Rdf := 0;
Z := 1;
N := 0;
V := Undefined
Exceptions:
None.