GMS30C2216 Datasheet, PDF (82/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

3-20
Register
L0 : $5678
L1 : $1234
L2 : $9ABC
Instruction
MULL0, L2
MULU
L0, L2
; L0 = $3443B020
; L0 = $0
; L1 = $3443B020
CHAPTER 3
3.13 Divide Instructions
The double-word destination operand (dividend) is divided by the single-word source
operand (divisor), the quotient is placed in the low-order destination register (Rdf), the
remainder is placed in the high-order destination register (Rd) and the condition flags are
set or cleared according to the quotient.
A trap to Range Error occurs if the divisor is zero or the value of the quotient exceeds the
integer value range (quotient overflow). The result (in Rd//Rdf) is then undefined. At
DIVS, a trap to Range Error also occurs and the result is undefined if the dividend is
negative.
At DIVS, the dividend is a non-negative signed double-word integer, the divisor, the
quotient and the remainder are signed integers; a non-zero remainder has the sign of the
dividend.
At DIVU, the dividend is an unsigned double-word integer, the divisor, the quotient and
the remainder are unsigned integers.
The result is undefined if Rs denotes the same register as Rd or Rdf or if the PC or the SR
is denoted.