GMS30C2216 Datasheet, PDF (144/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

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CHAPTER 6
6.9.3 Bus Signal Description
The following section describes the bus signals for both the GMS30C2232 and GMS30C2216
microprocessor in detail.
In the following signal description, the signal states are defined as I = input, O = output
and Z = three-state (inactive).
States Names
Use
I
XTAL1/CLKIN Input for quartz crystal. When the clock is generated by an
external clock generator, XTAL1 is used as clock input. The
clock signal is multiplied by four and divided according to the
TPR setting to generate the internal clock.
O XTAL2
Output for quartz crystal. XTAL2 is not connected when an
external clock generator is used.
O CLKOUT
Clock signal output or programmable output. CLKOUT can be
selected as a programmable output pin or as output delivering
the CPU clock signal divided by 1, 2 or 4. CLKOUT can be
used to supply a clock signal to peripheral devices.
O/Z A25..A0
The address bits A25..A0 represent the address bus. An active
high bit signals a "one". A0 is the least significant bit. With the
E1-16, only A21..A0 are connected to the address bus pins.
O/I D31..D0
Data bus. The signals D31..D0 (D15..D0 with the GMS30C2216)
represent the bidirectional data bus; active high signals a "one".
At a read access, data is transferred from the data bus to the
register set or to the instruction cache only at the cycle
corresponding to the last actual read access cycle, thus inhibiting
garbled data from being transferred.
At a write access, the data bus signals are activated during the
address setup, write and bus hold cycle(s).
A halfword or byte to be written is multiplexed from its right-
adjusted position in a register to the addressed halfword or byte
position. Thus, no external multiplexing of data signals is
required.
On a 32-bit wide memory area, byte addresses 0, 1, 2 and 3
correspond to D31..D24, D23..D16, D15..D8 and D7..D0
respectively (big endian).
On a 16-bit wide memory area, byte address 2 and 3 in the first
access and byte addresses 0 and 1 in the second access
correspond to D15..D8 and D7..D0 respectively.
On a 8-bit wide memory area, byte addresses 3..0 correspond to
D7..D0 in succeeding accesses.