GMS30C2216 Datasheet, PDF (142/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

6-26
CHAPTER 6
6.9 Bus Signals
6.9.1 Bus Signals for the GMS30C2232 Processor
The following table is an overview of the bus signals of the GMS30C2232 microprocessor.
For a detailed description of the function of the bus signals refer to section 6.9.3. Bus
Signal Description.
The signal states are defined as I = input, O = output and Z = three-state (inactive).
States
I
O
O
O/Z
O/I
O/I
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O/Z
O
I
O
I
I
O/I
I
I
Total:
Pin count Signal Name
Description
1
XTAL1/CLKIN
External Crystal, optionally Clock Input
1
XTAL2
External Crystal
1
CLKOUT
Clock Output
26
A25..A0
Address Bus
32
D31..D0
Data Bus
4
DP0..DP3
Parity bits
1
RAS#
DRAM RAS signal / Chip Select for MEM0
4
CAS0#..CAS3# DRAM CAS signal for bytes 0..3
1
WE#
Write Enable for DRAM and R/W# for I/O
3
CS1#..CS3#
Chip Select for MEM1..MEM3
4
WE0#..WE3#
Write Enable/Byte Enable for SRAM bytes 0..3
1
OE#
Output Enable for SRAMs, EPROMs, EDO DRAMs
1
IORD#
I/O Read Strobe, optionally I/O Data Strobe
1
IOWR#
I/O Write Strobe
1
RQST
Bus Request Output
1
GRANT#
Bus Grant Input
1
ACT
Active as Bus Master
3
INT1..INT2, INT4 Interrupt Inputs
1
INT3/WAIT
Interrupt Input or Wait Input
3
IO1..IO3
Programmable Input / Output
2
BOOTW, BOOTB Boot bus width selection inputs for MEM3
1
RESET#
Reset Input
16
NC
No Connect (not for GMS30C2232-144TQFP)
26
VDD
Power Supply Voltage
26
GND
Ground
160 (144 for GMS30C2232-144TQFP)
Table 6.9: Bus Signals for the GMS30C2232 Processor