GMS30C2216 Datasheet, PDF (210/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

A-38
Appendix A. Instruction Set Details
Halfword (complex) add/sub with fixed-point adjustment EHCFFTD
Format:
LLext format
15
87
43
0
OP-code
1100 1110
Ld-code
Ls-code
OP-code extention
0000 0000 1001 0110 (0x0096)
Ls-code encoded L0..L15 for Ls
Ld-code encoded L0..L15 for Ld
Notation:
EHCFFTD Ld, Ls
Description:
The extended DSP instruction uses on-chip multiply-accumulate unit. An Extended DSP
instruction is issued in one cycle; the processor starts execution of the next instruction
before the Extended DSP instruction is finished.
Double-word results are always placed in G14 and G15. The condition flags remain
unchanged
Ls does not used and should denote he same register.
This instruction can cause a n Extended Overflow exception when the Extended Overflow
Exception flag is enabled (FCR(16) = 0). Note that this overflow occurs asynchronously to
the execution of the Extended DSP instruction and any succeeding instructions.
Operation:
G14(31..16) ;= Ld(31..16) + (G14 >> 15);
G14(15..0) ;= Ld(15..0) + (G15 >> 15);
G15(31..16) ;= Ld(31..16) - (G14 >> 15);
G15(15..0) ;= Ld(15..0) - (G15 >> 15);
Exceptions:
Extended Overflow Exception