GMS30C2216 Datasheet, PDF (32/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

1-12
CHAPTER 1
FP
Frame Pointer. Bits 31..25 represent the frame pointer FP. The least significant
six bits of the FP point to the beginning of the current stack frame in the local
register set, that is, they point to L0.
The FP contains bit 8..2 of the address at which the content of L0 would be
stored if pushed onto the memory part of the stack.
1.2.3 Floating-Point Exception Register FER, G2
G2 is the floating-point exception register. All bits must be cleared to zero after Reset.
Only bits 12..8 and 4..0 may be changed by a user program, all other bits must remain
unchanged.
31
13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
Reserved for Operating System
Floating-Point Actual Exceptions
Floating-Point Accrued Exceptions
Figure 1.8: Floating-Point Exception Register
The floating-point trap enable flags FTE and the exception flags are assigned as:
floating-point
trap enable
FTE
SR(12)
SR(11)
Accrued
exceptions
G2(4)
G2(3)
Actual
exceptions
G2(12)
G2(11)
exception type
Invalid Operation
Division by Zero
SR(10)
SR(9)
SR(8)
G2(2)
G2(1)
G2(0)
G2(10)
G2(9)
G2(8)
Overflow
Underflow
Inexact
The reserved bits G2(31..13) and G2(7..5) must be zero.
A floating-point instruction, except a Floating-point Compare, can raise any of the
exceptions Invalid Operation, Division by Zero, Overflow, Underflow or Inexact. FCMP
and FCMPD can raise only the Invalid Operation exception (at unordered). FCMPU and
FCMPUD cannot raise any exception.