GMS30C2216 Datasheet, PDF (124/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

6-8
CHAPTER 6
6.1.1 Boot Width Selection
The processor provides two pins (BOOTW and BOOTB) for selecting the data bus width
for memory area MEM3 (boot memory area). Table 6.2 shows the encoding for selecting
the desired data bus width. The pin state is sampled during reset.
BOOTW
BOOTB
Data Bus Width
Don’ t care
HIGH
8-bit
LOW
LOW
16-bit
HIGH
LOW
32-bit
Table 6.2: Data bus width encoding for memory area MEM3
The pins used for BOOTB and BOOTW were used as VCC pins at the GMS30C2232 and
GMS30C2216.
Thus, if the GMS30C2232 is used as a direct replacement for the GMS30C2132, the
GMS30C2232 defaults to 8-bit MEM3 width as the GMS30C2132 did.
BOOTW is tied low internally for the GMS30C2216 processor, the BOOTB pin can then
be used to select between 8-bit and 16-bit MEM3 bus width.
6.1.2 SRAM and ROM Bus Access
On a one-cycle SRAM or EPROM read access, the output enable signal OE# is switched to
low during the second half of the access cycle; on a multi-cycle read access, OE# is
switched to low after the first access cycle and remains low through the rest of the
specified access cycles. On a SRAM write access, the write enable signals WE0#..WE3#
corresponding to the bytes to be written are switched to low analogous to the OE# signal
for single and multiple access cycles.
For memory area MEM2, an address setup cycle preceding the access cycles can be
specified. For MEM0..MEM3, bus hold cycles can be specified. Bus hold cycles are
additional cycles succeeding the access cycles where neither OE# nor WE0#..WE3# is low
but all other bus signals are asserted. The bus hold cycles can be specified to be skipped or
enforced. (see section 6.4.7. MEMx Bus Hold Break).