GMS30C2216 Datasheet, PDF (20/320 Pages) Hynix Semiconductor – 16/32 BIT RISC/DSP

0-10
CHAPTER 0
0.3.3 Pin Function
Type
Power
Clock
Address Bus
Data Bus
Bus Control
Name
VCC
GND
XTAL1
XTAL2
CLKOUT
A25..A0
D31..D0
DP0..DP3
RAS#
CAS0#..CAS3#
WE#
CS1#..CS3#
WE0#..WE3#
OE#
IORD#
Bus Control
IOWR#
RQST
GRANT#
ACT
Interrupt
INT1..INT4
I/O Port
IO1..IO3
System Control RESET#
State
Use
I Power. Connected to the power supply. It can be 3.3V power
supply.
I Ground. Connected to the system ground. All GND pins must
be connected to the system ground.
I Input for Quartz Clock. When the clock is generated by
external clock generator, XTAL1 is used as clock input.
O Output for Quartz Clock.
O Clock Signal Output. It can be used to supply a clock signal to
peripheral devices.
O/Z Address Bus. With the GMS30C2232, only A22..A0 are
connected to the address bus pins
I/O Data Bus. 32-bit bidirectional data bus
I/O Data Parity Signal. Bidirectional parity signals
O/Z Row Address Strobe. RAS# is activated when the processor
accesses a DRAM or refresh cycle. When a SRAM is placed in
MEM0, RAS# is used as the chip select signal
O/Z Column Address Strobe. They are only used by a DRAM for
column access cylices and for “CAS before RAS” refresh.
O/Z Write Enable. Active low indicates a write access, active high
indicates a read access.
O/Z Chip Select. Active low of CS1#..CS3# indicates chip select
for the memory areas MEM1..MEM3.
O/Z SRAM Write Enable. Active low indicates write enable for the
corresponding byte.
O/Z Output Enable for SRAMs and EPROMs.
O/Z I/O Read Strobe, optionally I/O Data Strobe. The use of
IORD# is specified in the I/O address bit 10.
O/Z I/O Write Strobe.
O RQST signals the request for a memory or I/O access
I Bus Grant. GRANT# is signaled low by an bus arbiter to grant
access to the bus for memory and I/O cycles
O Active as bus master. ACT is signaled high when GRANT# is
low and it is kept high during a current bus access
I Interrupt Request A signal of INT1..INT4 interrupt request
pins causes an interrupt exception when interrupt lock flag L is
clear and the corresponding INTxMask bit in FCR is not set.
I/O General Input-Output Port. IO1..IO3 can be individually
configured via IOxDirection bits in the FCR as either input or
output pins (port).
I Reset Processor. RESET# low resets the processor to the initial
state and halts all activity. RESET# must be low for at least
two cycles